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DP83869HM: SGMII to Cu 1000Base-T Configuration, Test and Operation

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869, , DP83869EVM

Simply stated, it does not work.  Although I have recently brought up a RGMII to Cu implementation using the DP83869 (same device) which does work.

The DP83869 is interfaced to a SJA1105S using SGMII.  Simple test data makes it as far as the SJA1105S's port 4, or so the counters say.

The DSP83869 has PhyAddr 0, and is strapped for OpMode210 = 110 (CPLD pulls thro 2k49), Aneg = 000, MirrorEn = 0 and LinkLoss = 'Z'

Both devices can be accessed to poke control and dump status registers using SMI / SPI.  Equally both devices have 25MHz clocks, observable as ClkOut.

One, minor, specific question is does the DP83869 have sgmii polarity reversal controls, the SJA1105 does and these have been set to normal for both Tx and Rx.

The core question is having exhausted the UM and ANs for ways ahead does one set to work the DP83869 ?

I gathered from a forum post that there are surprises undocumented in the manual, e.g. if one side wont talk the other keeps mum as well; deadly embrace ?

My last effort was to set the MAC loopback bit in register 0xC00 and look for returned traffic in the SJA1105, nothing seen.

The RJ45 interface is connected to a dumb switch (NetGear GS105) for test - auto negotiation does not succeed (based on the GS105s lites) [cable and GS105 pre checked].

As mentioned earlier the key questions are:

- what to check / tweak configuration wise

- what status indications to check

- which test modes and what settingsto use to prove the two external interfaces

Standing by

Martin

  • Hi,

    OPMode configuration used on your board "110" is correct for configuring the PHY for SGMII to Cu mode. Please confirm following:

    1. Are you able to link the Phy with Link Partner ? Status register 0x0001 can indicate you. If no, then I recomend reading register 0x01DF to confrim device is configured in correct mode.

    2. Is SGMII auto negotiation with SJAxxx device complete. This can be read from register 0x37.

    3. If step 2 is complete, then I would recomend to perform the MII Loopback test to ensure not issue on SGMII interface between SJAxx and DP83869HM

    Regards,
    geet

  • Geet

    Thank you for considering my problem and responding, I have conducted the steps you suggested and report them below (using your numbering).  In brief, the PHY has yet to fly.

    1. No, PhyReg 0001x = 7949x i.e. reset state, <2> is not set.  Equally PhyReg C001x reads 6149x.  PhyReg 1DFx reads 0046x, which I decode as SGMII to Cu and SGMII to RGMII bridge

    2. No, auto neg is not complete.  PhyReg 37x = 0000x, <0> the auto neg bit is clear

    3. no test, as step 2 fails

    FWIW the SJA1105S advises Rx link up SjaReg 1F0001 <2>, but auto neg is incomplete and the SGMII_LINK is reported down SjaReg 1F8001x <4> clear

    Therefore, it is probably best to prove the 1000BaseT side of the PHY "standalone" and then to re assess the SGMII link.  Can you suggest a suitable configuration ?

    Additionally, can you comment on the indication (elsewhere in this forum) that the 1000BaseT interface does not play until the SGMII interface is up; i.e. is this an issue ?

    I look forward to your recommendations for further testing

    Best Regards

    Martin

  • Hi Martin,

    0x1DF to 0x46 indicates PHY is configured in SGMII to Copper Mode.  However no link-up ( 0x0001) is more fundamental issue. 

    Are you using DP83869EVM or have your own board designed with DP83869HM ?

    How did you confirm "RGMII to Copper" Works ? Can you share little more details on your setup ?

    Regards,

    Geet

  • 20487000_ArCpu_Backplane_EnetR.pdf20489000_ArMux_Backplane_EnetR.pdf

    CPU_000_2020-04-13-172728.log
    =~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2020.04.13 17:27:28 =~=~=~=~=~=~=~=~=~=~=~=
    
    Cpu Test0 : Uart0&1 Enet etc ( Apr 13 2020 )
    
    CpuTest0_0 Silicon Version 3.1 (Code = 3)
    CpuTest0_0 Starting (built at Apr 13 2020 14:47:40) ...
    CpuTest0_0 MundungusInitialise - Initialising ScuTimer, Gic, ...
    CpuTest0_0 MundungusInitialise - Done
    [     0x] AE00030Ex
    Cpu SJA1105S - DeviceId prior : AE00030Ex 
    [     0x] 00000000x
    Cpu SJA1105S - DeviceId reset : 00000000x 
    [     1x] 00000000x
    Cpu SJA1105S - ConfigStatus   : 00000000x 
    [     0x] AE00030Ex
    Cpu SJA1105S - DeviceId post  : AE00030Ex 
    [     1x] 80000000x
    Cpu SJA1105S - ConfigStatus   : 80000000x 
    [   200x] 00000000x
    [   201x] 00000000x
    [   208x] 00000000x
    [   209x] 00000000x
    [   400x] 00000000x
    [   401x] 00000000x
    [   402x] 00000000x
    [   403x] 00000000x
    [   404x] 00000000x
    [   405x] 00000000x
    [   406x] 00000000x
    [   407x] 00000000x
    [   408x] 00000000x
    [   409x] 00000000x
    [   40Ax] 00000000x
    [   40Bx] 00000000x
    [   40Cx] 00000000x
    [   40Dx] 00000000x
    [   40Ex] 00000000x
    [   40Fx] 00000000x
    [   440x] 00000000x
    [   441x] 00000000x
    [   442x] 00000000x
    [   443x] 00000000x
    [   444x] 00000000x
    [   445x] 00000000x
    [   446x] 00000000x
    [   447x] 00000000x
    [   448x] 00000000x
    [   449x] 00000000x
    [   44Ax] 00000000x
    [   44Bx] 00000000x
    [   44Cx] 00000000x
    [   44Dx] 00000000x
    [   44Ex] 00000000x
    [   44Fx] 00000000x
    [   600x] 00000000x
    [   601x] 00000000x
    [   602x] 00000000x
    [   603x] 00000000x
    [   604x] 00000000x
    [   605x] 00000000x
    [   606x] 00000000x
    [   607x] 00000000x
    [   608x] 00000000x
    [   609x] 00000000x
    [   60Ax] 00000000x
    [   60Bx] 00000000x
    [   640x] 00000000x
    [   641x] 00000000x
    [   642x] 00000000x
    [   643x] 00000000x
    [   644x] 00000000x
    [   645x] 00000000x
    [   646x] 00000000x
    [   647x] 00000000x
    [   648x] 00000000x
    [   649x] 00000000x
    [   64Ax] 00000000x
    [   64Bx] 00000000x
    [  1400x] 00000000x
    [  1401x] 00000000x
    [  1402x] 00000000x
    [  1403x] 00000000x
    [  1404x] 00000000x
    [  1405x] 00000000x
    [  1406x] 00000000x
    [  1407x] 00000000x
    [  1408x] 00000000x
    [  1409x] 00000000x
    [  140Ax] 00000000x
    [  140Bx] 00000000x
    [  140Cx] 00000000x
    [  140Dx] 00000000x
    [  140Ex] 00000000x
    [  140Fx] 00000000x
    [  1410x] 00000000x
    [  1411x] 00000000x
    [  1412x] 00000000x
    [  1413x] 00000000x
    [  1414x] 00000000x
    [  1415x] 00000000x
    [  1416x] 00000000x
    [  1440x] 00000000x
    [  1441x] 00000000x
    [  1442x] 00000000x
    [  1443x] 00000000x
    [  1444x] 00000000x
    [  1445x] 00000000x
    [  1446x] 00000000x
    [  1447x] 00000000x
    [  1448x] 00000000x
    [  1449x] 00000000x
    [  144Ax] 00000000x
    [  144Bx] 00000000x
    [  144Cx] 00000000x
    [  144Dx] 00000000x
    [  144Ex] 00000000x
    [  144Fx] 00000000x
    [  1450x] 00000000x
    [  1451x] 00000000x
    [  1452x] 00000000x
    [  1453x] 00000000x
    [  1454x] 00000000x
    [  1455x] 00000000x
    [  1456x] 00000000x
    J2018 PHY detected at address 0 : Status1 = 7949x
    CpuTest0_0 SJA1105Initialise emac0 phy0 PhyId_2000_A0F1x Sts_7949x ExtSts_F000x
    CpuTest0_0 SJA1105Initialise TI Phy ID 2000x Detected - Configuration by DrB
    CpuTest0_0 Phy_J2018_Set_Speed phy0 Starting Autonegotiation
    CpuTest0_0 Phy_J2018_Set_Speed phy0 Phy reset completed after 0 ms
    PhyReg 0004x => 0DE1x
    PhyReg 0009x => 0300x
    CpuTest0_0 pre An Ti MdioRegister 000x = 1140x
    CpuTest0_0 pre An Ti MdioRegister 001x = 7949x
    CpuTest0_0 pre An Ti MdioRegister 002x = 2000x
    CpuTest0_0 pre An Ti MdioRegister 003x = A0F1x
    CpuTest0_0 pre An Ti MdioRegister 004x = 0DE1x
    CpuTest0_0 pre An Ti MdioRegister 005x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 006x = 0064x
    CpuTest0_0 pre An Ti MdioRegister 007x = 2001x
    CpuTest0_0 pre An Ti MdioRegister 008x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 009x = 0300x
    CpuTest0_0 pre An Ti MdioRegister 00Ax = 0000x
    CpuTest0_0 pre An Ti MdioRegister 00Bx = 0000x
    CpuTest0_0 pre An Ti MdioRegister 00Cx = 0000x
    CpuTest0_0 pre An Ti MdioRegister 00Dx = 401Fx
    CpuTest0_0 pre An Ti MdioRegister 00Ex = 0000x
    CpuTest0_0 pre An Ti MdioRegister 00Fx = F000x
    CpuTest0_0 pre An Ti MdioRegister 010x = 5048x
    CpuTest0_0 pre An Ti MdioRegister 011x = 0002x
    CpuTest0_0 pre An Ti MdioRegister 012x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 013x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 014x = 29C7x
    CpuTest0_0 pre An Ti MdioRegister 015x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 016x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 017x = 0040x
    CpuTest0_0 pre An Ti MdioRegister 018x = 6150x
    CpuTest0_0 pre An Ti MdioRegister 019x = 4444x
    CpuTest0_0 pre An Ti MdioRegister 01Ax = 0002x
    CpuTest0_0 pre An Ti MdioRegister 01Bx = 0000x
    CpuTest0_0 pre An Ti MdioRegister 01Cx = 0000x
    CpuTest0_0 pre An Ti MdioRegister 01Dx = 0000x
    CpuTest0_0 pre An Ti MdioRegister 01Ex = 0012x
    CpuTest0_0 pre An Ti MdioRegister 01Fx = 0000x
    CpuTest0_0 pre An Ti MdioRegister 025x = 0480x
    CpuTest0_0 pre An Ti MdioRegister 02Cx = 141Fx
    CpuTest0_0 pre An Ti MdioRegister 02Dx = 0000x
    CpuTest0_0 pre An Ti MdioRegister 02Ex = 0221x
    CpuTest0_0 pre An Ti MdioRegister 031x = 10B0x
    CpuTest0_0 pre An Ti MdioRegister 032x = 0050x
    CpuTest0_0 pre An Ti MdioRegister 033x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 037x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 039x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 03Ax = 0000x
    CpuTest0_0 pre An Ti MdioRegister 043x = 07A0x
    CpuTest0_0 pre An Ti MdioRegister 04Fx = 0176x
    CpuTest0_0 pre An Ti MdioRegister 06Ex = 0C00x
    CpuTest0_0 pre An Ti MdioRegister 086x = 0077x
    CpuTest0_0 pre An Ti MdioRegister 134x = 1000x
    CpuTest0_0 pre An Ti MdioRegister 135x = 0000x
    CpuTest0_0 pre An Ti MdioRegister 170x = 0C12x
    CpuTest0_0 pre An Ti MdioRegister 1DFx = 0046x
    CpuTest0_0 pre An Ti MdioRegister 1E0x = 417Ax
    CpuTest0_0 pre An Ti MdioRegister C00x = 1140x
    CpuTest0_0 pre An Ti MdioRegister C01x = 6149x
    CpuTest0_0 pre An Ti MdioRegister C02x = 2000x
    CpuTest0_0 pre An Ti MdioRegister C03x = A0F1x
    CpuTest0_0 pre An Ti MdioRegister C04x = 0020x
    CpuTest0_0 pre An Ti MdioRegister C05x = 0000x
    CpuTest0_0 pre An Ti MdioRegister C06x = 0000x
    CpuTest0_0 pre An Ti MdioRegister C07x = 2001x
    CpuTest0_0 pre An Ti MdioRegister C08x = 0000x
    CpuTest0_0 pre An Ti MdioRegister C18x = 01FFx
    CpuTest0_0 pre An Ti MdioRegister C19x = 0000x
    PhyReg C000x => 1340x
    PhyReg C001x => 7949x
    PhyReg 0000x => 0140x
    PhyReg 0000x => 1340x
    PhyReg 0000x => 1140x
    PhyReg 0001x => 7949x
    CpuTest0_0 Phy_J2018_Set_Speed phy0 Waiting for PHY to complete autonegotiation
    CpuTest0_0 Phy_J2018_Set_Speed phy0 Autonegotiation timeout after 5000 ms
    CpuTest0_0 Aneg Fail Ti MdioRegister 000x = 1140x
    CpuTest0_0 Aneg Fail Ti MdioRegister 001x = 7949x
    CpuTest0_0 Aneg Fail Ti MdioRegister 002x = 2000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 003x = A0F1x
    CpuTest0_0 Aneg Fail Ti MdioRegister 004x = 0DE1x
    CpuTest0_0 Aneg Fail Ti MdioRegister 005x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 006x = 0065x
    CpuTest0_0 Aneg Fail Ti MdioRegister 007x = 2001x
    CpuTest0_0 Aneg Fail Ti MdioRegister 008x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 009x = 0300x
    CpuTest0_0 Aneg Fail Ti MdioRegister 00Ax = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 00Bx = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 00Cx = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 00Dx = 401Fx
    CpuTest0_0 Aneg Fail Ti MdioRegister 00Ex = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 00Fx = F000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 010x = 5048x
    CpuTest0_0 Aneg Fail Ti MdioRegister 011x = 0302x
    CpuTest0_0 Aneg Fail Ti MdioRegister 012x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 013x = 0040x
    CpuTest0_0 Aneg Fail Ti MdioRegister 014x = 29C7x
    CpuTest0_0 Aneg Fail Ti MdioRegister 015x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 016x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 017x = 0040x
    CpuTest0_0 Aneg Fail Ti MdioRegister 018x = 6150x
    CpuTest0_0 Aneg Fail Ti MdioRegister 019x = 4444x
    CpuTest0_0 Aneg Fail Ti MdioRegister 01Ax = 0002x
    CpuTest0_0 Aneg Fail Ti MdioRegister 01Bx = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 01Cx = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 01Dx = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 01Ex = 0012x
    CpuTest0_0 Aneg Fail Ti MdioRegister 01Fx = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 025x = 0480x
    CpuTest0_0 Aneg Fail Ti MdioRegister 02Cx = 141Fx
    CpuTest0_0 Aneg Fail Ti MdioRegister 02Dx = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 02Ex = 0221x
    CpuTest0_0 Aneg Fail Ti MdioRegister 031x = 10B0x
    CpuTest0_0 Aneg Fail Ti MdioRegister 032x = 0050x
    CpuTest0_0 Aneg Fail Ti MdioRegister 033x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 037x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 039x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 03Ax = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 043x = 07A0x
    CpuTest0_0 Aneg Fail Ti MdioRegister 04Fx = 0176x
    CpuTest0_0 Aneg Fail Ti MdioRegister 06Ex = 0C00x
    CpuTest0_0 Aneg Fail Ti MdioRegister 086x = 0077x
    CpuTest0_0 Aneg Fail Ti MdioRegister 134x = 1000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 135x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister 170x = 0C12x
    CpuTest0_0 Aneg Fail Ti MdioRegister 1DFx = 0046x
    CpuTest0_0 Aneg Fail Ti MdioRegister 1E0x = 417Ax
    CpuTest0_0 Aneg Fail Ti MdioRegister C00x = 1140x
    CpuTest0_0 Aneg Fail Ti MdioRegister C01x = 6149x
    CpuTest0_0 Aneg Fail Ti MdioRegister C02x = 2000x
    CpuTest0_0 Aneg Fail Ti MdioRegister C03x = A0F1x
    CpuTest0_0 Aneg Fail Ti MdioRegister C04x = 0020x
    CpuTest0_0 Aneg Fail Ti MdioRegister C05x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister C06x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister C07x = 2001x
    CpuTest0_0 Aneg Fail Ti MdioRegister C08x = 0000x
    CpuTest0_0 Aneg Fail Ti MdioRegister C18x = 01FFx
    CpuTest0_0 Aneg Fail Ti MdioRegister C19x = 0000x
    CpuTest0_0 ReadEUI48 - Cpu 24AA02E48 EUI-48 = 80 1F 12 C8 D6 25
    CpuTest0_0 IPv4 Address   : 192.168.1.44
    CpuTest0_0 Subnet Mask    : 255.255.255.0
    CpuTest0_0 DefaultGateway : 192.168.1.1
    CpuTest0_0 Blinkenlites - '- - - - -   . . - - . .       '
    CpuTest0_0 lwip_init_timer - MEMP_NUM_SYS_TIMEOUT = 16
    CpuTest0_0 phy_setup phy0 Link speed = 1000 Mb/s
    CpuTest0_0 xemac_add completed
    CpuTest0_0 netif_set_default completed
    CpuTest0_0 SD_0 Initialised
    CpuTest0_0 SD_0 Input Clock 100000000 Hz
    CpuTest0_0 SD_0 BusWidth 0 CardDetect 1 WriteProtect 0
    CpuTest0_0 SD_0 HostCapabilities 69EC0080x
    CpuTest0_0 SD_0 HCS 1  CardType 1  CardVersion 2  CardConfigReg 0
    CpuTest0_0 SD_0 BusWidth 2  BusSpeed 50000000  BusMode 5
    CpuTest0_0 SD_0 Card SectorCount 121634816  CardId 00000133x 0000DABFx 00003634x 00005048x
    CpuTest0_0 FfsInitialise TotalSectors = 2100312 FreeSectors = 2094576
    CpuTest0_0 FfsInitialise uSD 0:/ file list ..
    CpuTest0_0 /BOOT.BIN ...
    CpuTest0_0 start_tftp_server tftp Server initialised and listening for client on port 69
    CpuTest0_0 00:00:32.022 start_tcp_tx_raw_server - TcpServer initialised and listening for client
    CpuTest0_0 connect_udp_tx_port Udp_SysLog Initialising ...
    CpuTest0_0 connect_udp_tx_port Udp_SysLog Udp Tx initialised on port 514
    CpuTest0_0 00:00:32.263 start_telnet_server - Initialising ...
    CpuTest0_0 00:00:32.330 start_telnet_server - Telnet server running on port 23
    CpuTest0_0 Blinkenlites - '- . - . -'
    CpuTest0_0 platform_enable_interrupts - Xil_ExceptionEnableMask completed
    CpuTest0_0 platform_enable_interrupts - XScuTimer_EnableInterrupt completed
    CpuTest0_0 platform_enable_interrupts - XScuTimer_Start completed
    CpuTest0_0 : platform_enable_interupts completed
    CpuTest0_0 : netif_set_up completed
    CpuTest0_0 Poke the keyboard and I will echo
    tcl> type_switch_status
    [   200x] 00000000x
    [   201x] 00000000x
    [   400x] 00000000x
    [   401x] 00000000x
    [   402x] 00000000x
    [   403x] 00000000x
    [   404x] 000002ACx
    [   405x] 00000000x
    [   406x] 00000008x
    [   407x] 00000000x
    [   408x] 00000000x
    [   409x] 00000000x
    [   40Ax] 00000000x
    [   40Bx] 00000000x
    [   40Cx] 00000000x
    [   40Dx] 00000000x
    [   40Ex] 00000000x
    [   40Fx] 00000000x
    [   600x] 00000000x
    [   601x] 00000000x
    [   602x] 00000000x
    [   603x] 00000000x
    [   604x] 00000000x
    [   605x] 00000000x
    [   606x] 00000000x
    [   607x] 00000000x
    [   608x] 00000000x
    [   609x] 00000000x
    [   60Ax] 00000000x
    [   60Bx] 00000000x
    [  1400x] 00000007x
    [  1401x] 00000001x
    [  1402x] 00000006x
    [  1403x] 00000000x
    [  1404x] 00000002x
    [  1405x] 00000000x
    [  1406x] 00000000x
    [  1407x] 00000000x
    [  1408x] 00000000x
    [  1409x] 00000000x
    [  140Ax] 00000000x
    [  140Bx] 00000000x
    [  140Cx] 00000000x
    [  140Dx] 00000000x
    [  140Ex] 00000000x
    [  140Fx] 00000000x
    [  1410x] 00000000x
    [  1411x] 00000000x
    [  1412x] 00000000x
    [  1413x] 00000000x
    [  1414x] 00000000x
    [  1415x] 00000000x
    [  1416x] 00000000x
    [   208x] 00000000x
    [   209x] 00000000x
    [   440x] 000002ACx
    [   441x] 00000000x
    [   442x] 00000008x
    [   443x] 00000000x
    [   444x] 00000000x
    [   445x] 00000000x
    [   446x] 00000000x
    [   447x] 00000000x
    [   448x] 00000000x
    [   449x] 00000000x
    [   44Ax] 00000000x
    [   44Bx] 00000000x
    [   44Cx] 00000000x
    [   44Dx] 00000000x
    [   44Ex] 00000000x
    [   44Fx] 00000000x
    [   640x] 00000000x
    [   641x] 00000000x
    [   642x] 00000000x
    [   643x] 00000000x
    [   644x] 00010000x
    [   645x] 00000000x
    [   646x] 00000000x
    [   647x] 00000000x
    [   648x] 00000000x
    [   649x] 00000000x
    [   64Ax] 00000000x
    [   64Bx] 00000000x
    [  1460x] 00000000x
    [  1461x] 00000000x
    [  1462x] 00000000x
    [  1463x] 00000000x
    [  1464x] 00000000x
    [  1465x] 00000000x
    [  1466x] 00000000x
    [  1467x] 00000000x
    [  1468x] 00000007x
    [  1469x] 00000001x
    [  146Ax] 00000006x
    [  146Bx] 00000000x
    [  146Cx] 00000002x
    [  146Dx] 00000000x
    [  146Ex] 00000000x
    [  146Fx] 00000000x
    [  1470x] 00000000x
    [  1471x] 00000000x
    [  1472x] 00000000x
    [  1473x] 00000000x
    [  1474x] 00000000x
    [  1475x] 00000000x
    [  1476x] 00000000x
    [100900x] 00363616x
    [100901x] 00313116x
    [100902x] 00313116x
    [100903x] 00313116x
    [100904x] 00313113x
    tcl> 
    tcl> type_switch_status 4
    [1F0000x] 00001140x
    [1F0001x] 00000189x
    [1F0002x] 00000000x
    [1F0003x] 00000000x
    [1F0004x] 00000020x
    [1F0005x] 00000000x
    [1F0006x] 00000000x
    [1F000Fx] 0000C000x
    [1F8000x] 00002400x
    [1F8001x] 00000004x
    [1F8002x] 0000000Ax
    [1F8003x] 00000000x
    [1F8005x] 00000000x
    [1F8010x] 00000010x
    [1F8011x] 000000FFx
    [1F8030x] 00000000x
    [1F8031x] 00000001x
    [1F8033x] 00000000x
    [1F8051x] 00000000x
    [1F8090x] 00000120x
    [1F80E1x] 00000010x
    [1F80E2x] 00000011x
    tcl> 
    
    MUX_000_2020-04-14-211805.log
    Test0 : Uart0&1 Enet etc ( Apr 14 2020 )
    
    
    MuxTest0_0 Silicon Version 3.1 (Code = 3)
    MuxTest0_0 Starting (built at Apr 14 2020 19:39:32) ...
    
    MuxTest0_0 MundungusInitialise - Initialising ScuTimer, Gic, ...
    
    MuxTest0_0 MundungusInitialise - Done
    
    MuxTest0_0 ReadEUI48 - Mux 24AA02E48 EUI-48 = 80 1F 12 C8 CD 08
    
    MuxTest0_0 IPv4 Address   : 192.168.1.44
    MuxTest0_0 Subnet Mask    : 255.255.255.0
    MuxTest0_0 DefaultGateway : 192.168.1.1
    MuxTest0_0 Blinkenlites - '- - - - -   . . - - . .       '
    
    MuxTest0_0 lwip_init_timer - MEMP_NUM_SYS_TIMEOUT = 16
    MuxTest0_0 detect_phy emac0 phy15 PhyId_2000_A0F1x Sts_7969x ExtSts_F000x
    MuxTest0_0 detect_phy TI Phy ID 2000x Detected - Configuration by DrB
    MuxTest0_0 get_TI_phy_speed phy15 Starting Autonegotiation
    MuxTest0_0 get_TI_phy_speed phy15 Phy reset completed after 0 ms
    
    MuxTest0_0 pre An Ti MdioRegister 000x = 1140x
    MuxTest0_0 pre An Ti MdioRegister 001x = 7949x
    MuxTest0_0 pre An Ti MdioRegister 002x = 2000x
    MuxTest0_0 pre An Ti MdioRegister 003x = A0F1x
    MuxTest0_0 pre An Ti MdioRegister 004x = 0DE1x
    MuxTest0_0 pre An Ti MdioRegister 005x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 006x = 0064x
    MuxTest0_0 pre An Ti MdioRegister 007x = 2001x
    MuxTest0_0 pre An Ti MdioRegister 008x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 009x = 0300x
    MuxTest0_0 pre An Ti MdioRegister 00Ax = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Bx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Cx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Dx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Ex = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Fx = F000x
    MuxTest0_0 pre An Ti MdioRegister 010x = 5048x
    MuxTest0_0 pre An Ti MdioRegister 011x = 0300x
    MuxTest0_0 pre An Ti MdioRegister 012x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 013x = 0042x
    MuxTest0_0 pre An Ti MdioRegister 014x = 29C7x
    MuxTest0_0 pre An Ti MdioRegister 015x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 016x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 017x = 0040x
    MuxTest0_0 pre An Ti MdioRegister 018x = 6150x
    MuxTest0_0 pre An Ti MdioRegister 019x = 4444x
    MuxTest0_0 pre An Ti MdioRegister 01Ax = 0002x
    MuxTest0_0 pre An Ti MdioRegister 01Bx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 01Cx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 01Dx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 01Ex = 0012x
    MuxTest0_0 pre An Ti MdioRegister 01Fx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 025x = 0480x
    MuxTest0_0 pre An Ti MdioRegister 02Cx = 141Fx
    MuxTest0_0 pre An Ti MdioRegister 02Dx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 02Ex = 0221x
    MuxTest0_0 pre An Ti MdioRegister 031x = 10B0x
    MuxTest0_0 pre An Ti MdioRegister 032x = 00D0x
    MuxTest0_0 pre An Ti MdioRegister 033x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 037x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 039x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 03Ax = 0000x
    MuxTest0_0 pre An Ti MdioRegister 043x = 07A0x
    MuxTest0_0 pre An Ti MdioRegister 04Fx = 0200x
    MuxTest0_0 pre An Ti MdioRegister 06Ex = 00F0x
    MuxTest0_0 pre An Ti MdioRegister 086x = 0077x
    MuxTest0_0 pre An Ti MdioRegister 134x = 1000x
    MuxTest0_0 pre An Ti MdioRegister 135x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 170x = 0C12x
    MuxTest0_0 pre An Ti MdioRegister 1DFx = 0040x
    MuxTest0_0 pre An Ti MdioRegister 1E0x = 417Ax
    MuxTest0_0 get_TI_phy_speed phy15 Waiting for PHY to complete autonegotiation
    MuxTest0_0 get_TI_phy_speed phy15 Autonegotiation successful after 2430 ms  DP83869HM (11x) PhyStatus = B802x
    
    MuxTest0_0 post An Ti MdioRegister 000x = 1140x
    MuxTest0_0 post An Ti MdioRegister 001x = 7969x
    MuxTest0_0 post An Ti MdioRegister 002x = 2000x
    MuxTest0_0 post An Ti MdioRegister 003x = A0F1x
    MuxTest0_0 post An Ti MdioRegister 004x = 0DE1x
    MuxTest0_0 post An Ti MdioRegister 005x = C5E1x
    MuxTest0_0 post An Ti MdioRegister 006x = 006Fx
    MuxTest0_0 post An Ti MdioRegister 007x = 2001x
    MuxTest0_0 post An Ti MdioRegister 008x = 5806x
    MuxTest0_0 post An Ti MdioRegister 009x = 0300x
    MuxTest0_0 post An Ti MdioRegister 00Ax = 3805x
    MuxTest0_0 post An Ti MdioRegister 00Bx = 0000x
    MuxTest0_0 post An Ti MdioRegister 00Cx = 0000x
    MuxTest0_0 post An Ti MdioRegister 00Dx = 401Fx
    MuxTest0_0 post An Ti MdioRegister 00Ex = 417Ax
    MuxTest0_0 post An Ti MdioRegister 00Fx = F000x
    MuxTest0_0 post An Ti MdioRegister 010x = 5048x
    MuxTest0_0 post An Ti MdioRegister 011x = AC02x
    MuxTest0_0 post An Ti MdioRegister 012x = 0000x
    MuxTest0_0 post An Ti MdioRegister 013x = 1D42x
    MuxTest0_0 post An Ti MdioRegister 014x = 29C7x
    MuxTest0_0 post An Ti MdioRegister 015x = 0000x
    MuxTest0_0 post An Ti MdioRegister 016x = 0000x
    MuxTest0_0 post An Ti MdioRegister 017x = 0040x
    MuxTest0_0 post An Ti MdioRegister 018x = 6150x
    MuxTest0_0 post An Ti MdioRegister 019x = 4444x
    MuxTest0_0 post An Ti MdioRegister 01Ax = 0002x
    MuxTest0_0 post An Ti MdioRegister 01Bx = 0000x
    MuxTest0_0 post An Ti MdioRegister 01Cx = 0000x
    MuxTest0_0 post An Ti MdioRegister 01Dx = 0000x
    MuxTest0_0 post An Ti MdioRegister 01Ex = 0012x
    MuxTest0_0 post An Ti MdioRegister 01Fx = 0000x
    MuxTest0_0 post An Ti MdioRegister 025x = 0480x
    MuxTest0_0 post An Ti MdioRegister 02Cx = 141Fx
    MuxTest0_0 post An Ti MdioRegister 02Dx = 0000x
    MuxTest0_0 post An Ti MdioRegister 02Ex = 0221x
    MuxTest0_0 post An Ti MdioRegister 031x = 10B0x
    MuxTest0_0 post An Ti MdioRegister 032x = 00D0x
    MuxTest0_0 post An Ti MdioRegister 033x = 0000x
    MuxTest0_0 post An Ti MdioRegister 037x = 0000x
    MuxTest0_0 post An Ti MdioRegister 039x = 0000x
    MuxTest0_0 post An Ti MdioRegister 03Ax = 0000x
    MuxTest0_0 post An Ti MdioRegister 043x = 07A0x
    MuxTest0_0 post An Ti MdioRegister 04Fx = 0200x
    MuxTest0_0 post An Ti MdioRegister 06Ex = 00F0x
    MuxTest0_0 post An Ti MdioRegister 086x = 0077x
    MuxTest0_0 post An Ti MdioRegister 134x = 1000x
    MuxTest0_0 post An Ti MdioRegister 135x = 0000x
    MuxTest0_0 post An Ti MdioRegister 170x = 0C12x
    MuxTest0_0 post An Ti MdioRegister 1DFx = 0040x
    MuxTest0_0 post An Ti MdioRegister 1E0x = 417Ax
    MuxTest0_0 phy_setup phy15 Link speed = 1000 Mb/s
    MuxTest0_0 xemac_add completed
    MuxTest0_0 netif_set_default completed
    MuxTest0_0 FfsInitialise f_mount fails = 3
    MuxTest0_0 start_tftp_server FfsInitialise returned error FR_3 The physical drive cannot work
    MuxTest0_0 00:20:35.010 start_tcp_tx_raw_server - TcpServer initialised and listening for client
    MuxTest0_0 connect_udp_tx_port Udp_SysLog Initialising ...
    MuxTest0_0 connect_udp_tx_port Udp_SysLog Udp Tx initialised on port 514
    MuxTest0_0 00:20:35.252 start_telnet_server - Initialising ...
    MuxTest0_0 00:20:35.319 start_telnet_server - Telnet server running on port 23
    MuxTest0_0 Blinkenlites - '- . - . -'
    
    MuxTest0_0 platform_enable_interrupts - Xil_ExceptionEnableMask completed
    
    MuxTest0_0 platform_enable_interrupts - XScuTimer_EnableInterrupt completed
    
    MuxTest0_0 platform_enable_interrupts - XScuTimer_Start completed
    
    MuxTest0_0 : platform_enable_interupts completed
    MuxTest0_0 : netif_set_up completed
    MuxTest0_0 Poke the keyboard and I will echo
    
    tcl> type_phy_status
    
    MuxTest0_0 00:30:35.414 Ti (11x) Link up
    MuxTest0_0 00:30:35.414 Ti (11x) PhySts   = AC02x
    MuxTest0_0 00:30:35.414 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:30:35.414 Ti (13x) IrqSts   = 0504x
    MuxTest0_0 00:30:35.414 Ti (0Ax) IdleErr  = 255
    MuxTest0_0 00:30:35.414 Ti (15x) RcvrErr  = 0
    tcl> 
    
    tcl> type_phy_status
    
    MuxTest0_0 00:30:43.222 Ti (11x) Link up
    MuxTest0_0 00:30:43.222 Ti (11x) PhySts   = AC02x
    MuxTest0_0 00:30:43.222 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:30:43.222 Ti (13x) IrqSts   = 0504x
    MuxTest0_0 00:30:43.222 Ti (0Ax) IdleErr  = 62
    MuxTest0_0 00:30:43.222 Ti (15x) RcvrErr  = 0
    tcl> 
    
    tcl> type_phy_status
    
    MuxTest0_0 00:30:45.606 Ti (11x) Link up
    MuxTest0_0 00:30:45.606 Ti (11x) PhySts   = AC02x
    MuxTest0_0 00:30:45.606 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:30:45.606 Ti (13x) IrqSts   = 0504x
    MuxTest0_0 00:30:45.606 Ti (0Ax) IdleErr  = 52
    MuxTest0_0 00:30:45.606 Ti (15x) RcvrErr  = 0
    tcl> get_phy_reg 0
    [0] 0x1140
    
    tcl> set_phy_reg 0 9140
    [0] 0x9140
    
    tcl> set_phy_reg 0 9140
    
    tcl> get_phy_reg 0
    
    tcl> type_phy_status
    
    MuxTest0_0 00:31:21.191 Ti (11x) Link up
    MuxTest0_0 00:31:21.191 Ti (11x) PhySts   = BC02x
    MuxTest0_0 00:31:21.191 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:31:21.191 Ti (13x) IrqSts   = 1D46x
    MuxTest0_0 00:31:21.191 Ti (0Ax) IdleErr  = 255
    MuxTest0_0 00:31:21.191 Ti (15x) RcvrErr  = 0
    
    tcl> type_phy_status
    
    tcl> set_phy_reg 0 9140
    [0] 0x9140
    
    tcl> type_phy_status
    
    MuxTest0_0 00:31:42.967 Ti (11x) Link up
    MuxTest0_0 00:31:42.967 Ti (11x) PhySts   = BC02x
    MuxTest0_0 00:31:42.967 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:31:42.967 Ti (13x) IrqSts   = 1D44x
    MuxTest0_0 00:31:42.967 Ti (0Ax) IdleErr  = 255
    MuxTest0_0 00:31:42.967 Ti (15x) RcvrErr  = 0
    
    tcl> set_phy_reg 0 9140
    
    tcl> type_phy_status
    
    MuxTest0_0 00:32:20.975 Ti (11x) Link up
    MuxTest0_0 00:32:20.975 Ti (11x) PhySts   = 7C02x
    MuxTest0_0 00:32:20.975 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:32:20.975 Ti (13x) IrqSts   = DD46x
    MuxTest0_0 00:32:20.975 Ti (0Ax) IdleErr  = 0
    MuxTest0_0 00:32:20.975 Ti (15x) RcvrErr  = 0
    
    tcl> type_phy_regs
    
    MuxTest0_0 00:32:43.304 Ti MdioRegister 000x = 1140x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 001x = 7969x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 002x = 2000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 003x = A0F1x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 004x = 01E1x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 005x = C5E1x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 006x = 006Fx
    MuxTest0_0 00:32:43.304 Ti MdioRegister 007x = 2001x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 008x = 7801x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 009x = 0300x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 00Ax = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 00Bx = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 00Cx = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 00Dx = 401Fx
    MuxTest0_0 00:32:43.304 Ti MdioRegister 00Ex = 417Ax
    MuxTest0_0 00:32:43.304 Ti MdioRegister 00Fx = F000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 010x = 5048x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 011x = 6C02x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 012x = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 013x = 0004x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 014x = 29C7x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 015x = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 016x = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 017x = 0040x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 018x = 6150x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 019x = 4444x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 01Ax = 0002x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 01Bx = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 01Cx = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 01Dx = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 01Ex = 0012x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 01Fx = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 025x = 0480x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 02Cx = 141Fx
    MuxTest0_0 00:32:43.304 Ti MdioRegister 02Dx = 2000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 02Ex = 0221x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 031x = 10B0x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 032x = 10D0x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 033x = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 037x = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 039x = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 03Ax = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 043x = 07A0x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 04Fx = 0200x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 06Ex = 00F0x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 086x = 0077x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 134x = 1000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 135x = 0000x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 170x = 0C12x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 1DFx = 0040x
    MuxTest0_0 00:32:43.304 Ti MdioRegister 1E0x = 417Ax
    tcl> 
    
    MUX_001_2020-04-14-221039.log
    =~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2020.04.14 22:10:39 =~=~=~=~=~=~=~=~=~=~=~=
    Test0 : Uart0&1 Enet etc ( Apr 14 2020 )
    
    
    MuxTest0_0 Silicon Version 3.1 (Code = 3)
    MuxTest0_0 Starting (built at Apr 14 2020 19:39:32) ...
    
    MuxTest0_0 MundungusInitialise - Initialising ScuTimer, Gic, ...
    
    MuxTest0_0 MundungusInitialise - Done
    
    MuxTest0_0 ReadEUI48 - Mux 24AA02E48 EUI-48 = 80 1F 12 C8 E1 60
    
    MuxTest0_0 IPv4 Address   : 192.168.1.44
    MuxTest0_0 Subnet Mask    : 255.255.255.0
    MuxTest0_0 DefaultGateway : 192.168.1.1
    MuxTest0_0 Blinkenlites - '- - - - -   . . - - . .       '
    
    MuxTest0_0 lwip_init_timer - MEMP_NUM_SYS_TIMEOUT = 16
    MuxTest0_0 detect_phy emac0 phy15 PhyId_2000_A0F1x Sts_7969x ExtSts_F000x
    MuxTest0_0 detect_phy TI Phy ID 2000x Detected - Configuration by DrB
    MuxTest0_0 get_TI_phy_speed phy15 Starting Autonegotiation
    MuxTest0_0 get_TI_phy_speed phy15 Phy reset completed after 0 ms
    
    MuxTest0_0 pre An Ti MdioRegister 000x = 1140x
    MuxTest0_0 pre An Ti MdioRegister 001x = 7949x
    MuxTest0_0 pre An Ti MdioRegister 002x = 2000x
    MuxTest0_0 pre An Ti MdioRegister 003x = A0F1x
    MuxTest0_0 pre An Ti MdioRegister 004x = 0DE1x
    MuxTest0_0 pre An Ti MdioRegister 005x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 006x = 0064x
    MuxTest0_0 pre An Ti MdioRegister 007x = 2001x
    MuxTest0_0 pre An Ti MdioRegister 008x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 009x = 0300x
    MuxTest0_0 pre An Ti MdioRegister 00Ax = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Bx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Cx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Dx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Ex = 0000x
    MuxTest0_0 pre An Ti MdioRegister 00Fx = F000x
    MuxTest0_0 pre An Ti MdioRegister 010x = 5048x
    MuxTest0_0 pre An Ti MdioRegister 011x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 012x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 013x = 0042x
    MuxTest0_0 pre An Ti MdioRegister 014x = 29C7x
    MuxTest0_0 pre An Ti MdioRegister 015x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 016x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 017x = 0040x
    MuxTest0_0 pre An Ti MdioRegister 018x = 6150x
    MuxTest0_0 pre An Ti MdioRegister 019x = 4444x
    MuxTest0_0 pre An Ti MdioRegister 01Ax = 0002x
    MuxTest0_0 pre An Ti MdioRegister 01Bx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 01Cx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 01Dx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 01Ex = 0012x
    MuxTest0_0 pre An Ti MdioRegister 01Fx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 025x = 0480x
    MuxTest0_0 pre An Ti MdioRegister 02Cx = 141Fx
    MuxTest0_0 pre An Ti MdioRegister 02Dx = 0000x
    MuxTest0_0 pre An Ti MdioRegister 02Ex = 0221x
    MuxTest0_0 pre An Ti MdioRegister 031x = 10B0x
    MuxTest0_0 pre An Ti MdioRegister 032x = 00D0x
    MuxTest0_0 pre An Ti MdioRegister 033x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 037x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 039x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 03Ax = 0000x
    MuxTest0_0 pre An Ti MdioRegister 043x = 07A0x
    MuxTest0_0 pre An Ti MdioRegister 04Fx = 0200x
    MuxTest0_0 pre An Ti MdioRegister 06Ex = 00F0x
    MuxTest0_0 pre An Ti MdioRegister 086x = 0077x
    MuxTest0_0 pre An Ti MdioRegister 134x = 1000x
    MuxTest0_0 pre An Ti MdioRegister 135x = 0000x
    MuxTest0_0 pre An Ti MdioRegister 170x = 0C0Fx
    MuxTest0_0 pre An Ti MdioRegister 1DFx = 0040x
    MuxTest0_0 pre An Ti MdioRegister 1E0x = 417Ax
    MuxTest0_0 get_TI_phy_speed phy15 Waiting for PHY to complete autonegotiation
    MuxTest0_0 get_TI_phy_speed phy15 Autonegotiation successful after 3081 ms  DP83869HM (11x) PhyStatus = BB02x
    
    MuxTest0_0 post An Ti MdioRegister 000x = 1140x
    MuxTest0_0 post An Ti MdioRegister 001x = 7969x
    MuxTest0_0 post An Ti MdioRegister 002x = 2000x
    MuxTest0_0 post An Ti MdioRegister 003x = A0F1x
    MuxTest0_0 post An Ti MdioRegister 004x = 0DE1x
    MuxTest0_0 post An Ti MdioRegister 005x = C5E1x
    MuxTest0_0 post An Ti MdioRegister 006x = 006Fx
    MuxTest0_0 post An Ti MdioRegister 007x = 2001x
    MuxTest0_0 post An Ti MdioRegister 008x = 5806x
    MuxTest0_0 post An Ti MdioRegister 009x = 0300x
    MuxTest0_0 post An Ti MdioRegister 00Ax = 28B5x
    MuxTest0_0 post An Ti MdioRegister 00Bx = 0000x
    MuxTest0_0 post An Ti MdioRegister 00Cx = 0000x
    MuxTest0_0 post An Ti MdioRegister 00Dx = 401Fx
    MuxTest0_0 post An Ti MdioRegister 00Ex = 417Ax
    MuxTest0_0 post An Ti MdioRegister 00Fx = F000x
    MuxTest0_0 post An Ti MdioRegister 010x = 5048x
    MuxTest0_0 post An Ti MdioRegister 011x = AB02x
    MuxTest0_0 post An Ti MdioRegister 012x = 0000x
    MuxTest0_0 post An Ti MdioRegister 013x = 1D42x
    MuxTest0_0 post An Ti MdioRegister 014x = 29C7x
    MuxTest0_0 post An Ti MdioRegister 015x = 0000x
    MuxTest0_0 post An Ti MdioRegister 016x = 0000x
    MuxTest0_0 post An Ti MdioRegister 017x = 0040x
    MuxTest0_0 post An Ti MdioRegister 018x = 6150x
    MuxTest0_0 post An Ti MdioRegister 019x = 4444x
    MuxTest0_0 post An Ti MdioRegister 01Ax = 0002x
    MuxTest0_0 post An Ti MdioRegister 01Bx = 0000x
    MuxTest0_0 post An Ti MdioRegister 01Cx = 0000x
    MuxTest0_0 post An Ti MdioRegister 01Dx = 0000x
    MuxTest0_0 post An Ti MdioRegister 01Ex = 0012x
    MuxTest0_0 post An Ti MdioRegister 01Fx = 0000x
    MuxTest0_0 post An Ti MdioRegister 025x = 0480x
    MuxTest0_0 post An Ti MdioRegister 02Cx = 141Fx
    MuxTest0_0 post An Ti MdioRegister 02Dx = 0000x
    MuxTest0_0 post An Ti MdioRegister 02Ex = 0221x
    MuxTest0_0 post An Ti MdioRegister 031x = 10B0x
    MuxTest0_0 post An Ti MdioRegister 032x = 00D0x
    MuxTest0_0 post An Ti MdioRegister 033x = 0000x
    MuxTest0_0 post An Ti MdioRegister 037x = 0000x
    MuxTest0_0 post An Ti MdioRegister 039x = 0000x
    MuxTest0_0 post An Ti MdioRegister 03Ax = 0000x
    MuxTest0_0 post An Ti MdioRegister 043x = 07A0x
    MuxTest0_0 post An Ti MdioRegister 04Fx = 0200x
    MuxTest0_0 post An Ti MdioRegister 06Ex = 00F0x
    MuxTest0_0 post An Ti MdioRegister 086x = 0077x
    MuxTest0_0 post An Ti MdioRegister 134x = 1000x
    MuxTest0_0 post An Ti MdioRegister 135x = 0000x
    MuxTest0_0 post An Ti MdioRegister 170x = 0C0Fx
    MuxTest0_0 post An Ti MdioRegister 1DFx = 0040x
    MuxTest0_0 post An Ti MdioRegister 1E0x = 417Ax
    MuxTest0_0 phy_setup phy15 Link speed = 1000 Mb/s
    MuxTest0_0 xemac_add completed
    MuxTest0_0 netif_set_default completed
    MuxTest0_0 FfsInitialise f_mount fails = 3
    MuxTest0_0 start_tftp_server FfsInitialise returned error FR_3 The physical drive cannot work
    MuxTest0_0 00:12:02.297 start_tcp_tx_raw_server - TcpServer initialised and listening for client
    MuxTest0_0 connect_udp_tx_port Udp_SysLog Initialising ...
    MuxTest0_0 connect_udp_tx_port Udp_SysLog Udp Tx initialised on port 514
    MuxTest0_0 00:12:02.538 start_telnet_server - Initialising ...
    MuxTest0_0 00:12:02.605 start_telnet_server - Telnet server running on port 23
    MuxTest0_0 Blinkenlites - '- . - . -'
    
    MuxTest0_0 platform_enable_interrupts - Xil_ExceptionEnableMask completed
    
    MuxTest0_0 platform_enable_interrupts - XScuTimer_EnableInterrupt completed
    
    MuxTest0_0 platform_enable_interrupts - XScuTimer_Start completed
    
    MuxTest0_0 : platform_enable_interupts completed
    MuxTest0_0 : netif_set_up completed
    MuxTest0_0 Poke the keyboard and I will echo
    
    tcl> type_phy_status
    
    MuxTest0_0 00:12:29.206 Ti (11x) Link up
    MuxTest0_0 00:12:29.206 Ti (11x) PhySts   = 7C02x
    MuxTest0_0 00:12:29.206 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:12:29.206 Ti (13x) IrqSts   = 5D44x
    MuxTest0_0 00:12:29.206 Ti (0Ax) IdleErr  = 0
    MuxTest0_0 00:12:29.206 Ti (15x) RcvrErr  = 0
    
    tcl> type_phy_status
    
    MuxTest0_0 00:12:41.046 Ti (11x) Link up
    MuxTest0_0 00:12:41.046 Ti (11x) PhySts   = 6C02x
    MuxTest0_0 00:12:41.046 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:12:41.046 Ti (13x) IrqSts   = 0004x
    MuxTest0_0 00:12:41.046 Ti (0Ax) IdleErr  = 0
    MuxTest0_0 00:12:41.046 Ti (15x) RcvrErr  = 0
    
    tcl> type_phy_status
    
    MuxTest0_0 00:13:14.791 Ti (11x) Link up
    MuxTest0_0 00:13:14.791 Ti (11x) PhySts   = 6C02x
    MuxTest0_0 00:13:14.791 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:13:14.791 Ti (13x) IrqSts   = 0004x
    MuxTest0_0 00:13:14.791 Ti (0Ax) IdleErr  = 0
    MuxTest0_0 00:13:14.791 Ti (15x) RcvrErr  = 0
    
    tcl> set_phy_reg 0 9140
    
    tcl> type_phy_status
    
    MuxTest0_0 00:15:48.962 Ti (11x) Link up
    MuxTest0_0 00:15:48.962 Ti (11x) PhySts   = 7C02x
    MuxTest0_0 00:15:48.962 Ti (10x) PhyCtrl  = 5048x
    MuxTest0_0 00:15:48.962 Ti (13x) IrqSts   = 5D44x
    MuxTest0_0 00:15:48.962 Ti (0Ax) IdleErr  = 0
    MuxTest0_0 00:15:48.962 Ti (15x) RcvrErr  = 0
    tcl> type_phy_regs
    
    MuxTest0_0 00:19:44.063 Ti MdioRegister 000x = 1140x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 001x = 7969x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 002x = 2000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 003x = A0F1x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 004x = 01E1x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 005x = C5E1x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 006x = 006Fx
    MuxTest0_0 00:19:44.063 Ti MdioRegister 007x = 2001x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 008x = 7801x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 009x = 0300x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 00Ax = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 00Bx = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 00Cx = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 00Dx = 401Fx
    MuxTest0_0 00:19:44.063 Ti MdioRegister 00Ex = 417Ax
    MuxTest0_0 00:19:44.063 Ti MdioRegister 00Fx = F000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 010x = 5048x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 011x = 6C02x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 012x = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 013x = 0004x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 014x = 29C7x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 015x = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 016x = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 017x = 0040x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 018x = 6150x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 019x = 4444x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 01Ax = 0002x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 01Bx = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 01Cx = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 01Dx = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 01Ex = 0012x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 01Fx = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 025x = 0480x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 02Cx = 141Fx
    MuxTest0_0 00:19:44.063 Ti MdioRegister 02Dx = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 02Ex = 0221x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 031x = 10B0x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 032x = 50D0x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 033x = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 037x = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 039x = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 03Ax = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 043x = 07A0x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 04Fx = 0200x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 06Ex = 00F0x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 086x = 0077x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 134x = 1000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 135x = 0000x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 170x = 0C0Fx
    MuxTest0_0 00:19:44.063 Ti MdioRegister 1DFx = 0040x
    MuxTest0_0 00:19:44.063 Ti MdioRegister 1E0x = 417Ax
    
    tcl> syslog_info "good evening"
    tcl> type_lwip_status
    
    MuxTest0_0 00:26:14.335 Lwip Link   84t 0r 0f 0d 0c 0l 0m 0r 0p 0o 0e 0h
    MuxTest0_0 00:26:14.349 Lwip EthArp 80t 0r 0f 0d 0c 0l 0m 0r 0p 0o 0e 0h
    MuxTest0_0 00:26:14.426 Lwip Ip     83t 0r 0f 0d 0c 0l 0m 0r 0p 0o 0e 0h
    MuxTest0_0 00:26:14.503 Lwip Udp    82t 0r 0f 0d 0c 0l 0m 0r 0p 0o 0e 0h
    MuxTest0_0 00:26:14.580 Lwip Tcp    0t 0r 0f 0d 0c 0l 0m 0r 0p 0o 0e 0h
    MuxTest0_0 00:26:14.656 Lwip Mem    131072a 640u 1664m
    MuxTest0_0 00:26:14.714 Lwip MemR   16a 0u 0m
    MuxTest0_0 00:26:14.763 Lwip MemP   8192a 64u 65m
    tcl>
    
    

    Hi Geet

    We have our own boards using the DP83869HM - extracts from their schematics are attached.  The uC is a Zynq 7Z020 with several Lattice XO2s in support.  The RJ45 is a TE 2301995-4.  The 25 MHz clock is sourced from a 50 MHz 20 ppm MEMS and delivered via a PLL.  The resets (certainly in the case of the CPU) observe the 200 ms hold after power stable.

    Specimen console logs are provided for CPU_000 hard fail and the subject of the preceeding eMails.  MUX_000 and MUX_001 turn out to have a range of interesting tricks, including auto neg ing both ends of the link to different speeds (lites on GS105) - there is a hint of this in the logs.  So much for RGMII to Cu works - there has been some traffic passed ...

    Best Regards and standing by

    Martin

  • Hi Martin,

    I was looking at logfile "CPU_0000_2020...xx". Register 0x0005 and 0x000A indicates Link Partner capabilities for Auto-Negotiation. Both the registers have 0x00. 

    It indicates Phy is not recieving any information from Link Partner to form the link. It can be for following reason:

    1. RJ-45 connections are in Mirror mode. means DUT is transmiiting FLP pulse on channel A & B while Link Partner on C & D. You can try enabling Mirror mode and see if it helps.

    2. The clock provided to PHY is of not good quality. Datasheet has input clock tolerance specified. You may want to measure the 25 MHz input clock quality to check this.

    Regards,
    Geet