Hi All,
Could you help to confirm the calculation of the CLK_OUT is correct because the result of example 2 is different from the datasheet?
Refer to the example 2 (EF F => 25MHz, M => 1 (0X01), N => 30 (0X1E), HS_CLK_DIV => 4),
our result is 33.33MHz which is different from 37.037 of Datasheet.
Attached our block diagram for your reference.
If possible, would you help to provide the upper and lower limits that could be set for the values of M and N.