This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi All,
Could you help to confirm the calculation of the CLK_OUT is correct because the result of example 2 is different from the datasheet?
Refer to the example 2 (EF F => 25MHz, M => 1 (0X01), N => 30 (0X1E), HS_CLK_DIV => 4),
our result is 33.33MHz which is different from 37.037 of Datasheet.
Attached our block diagram for your reference.
If possible, would you help to provide the upper and lower limits that could be set for the values of M and N.
Hello Jackie,
Based on the settings you provided above, the 33.3MHz CLK_OUT is correct so I'm not sure what you mean:
FC = 25MHz*160 = 4Gbps
M = 1
N = 30
HS_CLK_DIV = 4
CLK_OUT = FC*(M/(N*HS_CLK_DIV)) = 33.3MHz
Best Regards,
Casey
Hello Jackie,
Thank you for pointing this out. The datasheet appears to have a typo. The N value should be 0x1B in that example, not 0x1E. We will flag it for the next datasheet update.
For the min and max values we would have to check to see if we have any characterization data
Best Regards,
Casey
Hey Jackie,
For the CLK_OUT limit, the resultant frequency must be less than 100MHz.
M value must be in range 1-31 and N value must be in range 1-255.
Best Regards,
Casey