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DP83869HM: Bridge RGMII to SGMII, MAC to MAC configuration

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Hi,


I'm trying to use the DP83869HM as a bridge RGMII to SGMII (from an ASIC (MAC) to a micro-proc (MAC)).
I'm facing some trouble with the configuration.  First of all, I can't get the link status with the auto-negotiation enable.
I checked the register OP_MODE_CODE (0x1DF) and tried the values 0x43 and 0x03 (RGMII to SGMII or SGMII to RGMII)
I set differents registers in order to get 125 MHz on CLK_OUT: REG (0x170) = 0x800 and REG (0xC6) = 0x10. I got the correct CLK_OUT at 125 MHz. But I can't get 125 MHz on RX_CLK because (I think) of the link status down.

So, I looking for some help on the configuration, thanks.

BR,

Julien

DP83869HM

  • Hi Julien,

    Which MAC interface do you want to select the operating speed of in bridge mode? In RGMII-to-SGMII the SGMII MAC will select the operating speed and adjust RGMII accordingly. 

    Can you confirm you've written register 0x0C00=0x1140 after configuring register 0x1DF?

    How are you determining link status? 

    Please also note that there is an error in the datasheet when setting the device into Bridge mode through register configuration: 

    The description in Bit 6 of OP_MODE_DECODE register 0x1DF is wrong. It should be flipped as shown below:

    0x1 = RGMII to SGMII Bridge
    0x0 = SGMII to RGMII Bridge

    Regards,
    Justin 

  • Hi Justin,

    Thanks you for your answer.

    Yes, I suppose that the MAC SGMII operate the speed in gigabit so I wrote REG(0x1DF)=0x43. (But, I tried both configuration REG(0x1DF)=0X03, since I found the error of the register 0x1DF in the forum...)

    Yes, I confirm I wrote REG(0xC00)=0x1140 after configuring register 0x1DF.

    I'm using the register BMSR bit 2 to get the "link status" and bit 5 for the "autoneg comp" and both are 0.

    I found in the documentation: "In case where the PHY is does not have a link, the RGMII clock frequency will default to 2.5 MHz.", so I can not get 125MHz on RX_CLK.

    Thanks a lot for your help,

    BR,

    Julien

  • Hi Julien,

    In RGMII-to-SGMII Bridge mode of the DP83869 is expecting a PHY connected to the SGMII interface. This means the SGMII may not be able to auto-negotiate with a MAC connected to the SGMII interface. 

    You can set the DP83869 to disable SGMII auto-negotiation through register 0x14[bit 9]=0. 

    Regards,

    Justin 

  • Hi Justin,

    Thanks you for your answer.

    Okay, that's unfortunately what I assumed. Yes, I tried the 0x14 register without good results. And I'm still stuck with a 2.5 MHz RX_CLK.

    Thanks,

    BR,

    Julien

  • (Correction bit 7 of reg(0x14): SGMII_AUTONEG_EN)

  • Hi Julien,

    You can also try to extend the SGMII Auto-negotiation timer in register 0x0031[6:5]=11. Some MACs cannot react fast enough in the 2us before auto-negotiation will restart. 

    You should provide a soft reset of 0x001F=0x4000 after changing these registers to reset the PHY with the updated register configurations as well.

    Is it possible to connect the use SGMII-to-RGMII bridge mode and connect RGMII interface to get link and speed information? 

    Regards,

    Justin 

  • Hi Justin,

    Thanks you for your answer.

    I have tried this morning the REG(0x31)=0x60 and make a software reset without good result.

    Unfortunatly, I can't use the RGMII to get link because (I think) I can't get the correct clock on RX_CLK.

    Thanks again,

    BR,

    Julien

  • Hi Justin,

    I'm still trying to fix this problem but I can't get auto-negotiation on SGMII (and RGMII). The MAC SGMII cannot make negotiations because of an errata in the component P1010 ...

    Do you think it is possible to define the RGMII link in gigabits? and have the RX_CLK at 125 MHz by configuring the PHY registers? (without link status)

    Or force the link status ON?

    Thanks you,

    BR,

    Julien

  • Hi Julien,

    In SGMII-to-RGMII bridge mode, the DP83869 is acting as an RGMII MAC to the connected RGMII PHY (or in your case, another MAC). The RGMII PHY will need to send the 125MHz clock to the DP83869 in order to create a link. 

    Regards,
    Justin 

  • Hi Justin,

    Here are the clocks signals connected to the DP83869 :

    -       TX_CLK from the RGMII MAC to the DP83869 at 125 MHz (OK)

    -       CLK_OUT from the DP83869 to the RGMII and SGMII MACs at 125MHz(Ok, if the register 0xC6 is written to 0x10)

    -       RX_CLK from the DP83869 to the RGMII MAX at 125 MHz è KO, RX_CLK is stuck at 2.5 MHz

    Before getting any further and trying to exchange frames, I was trying to get the clocks working at the right frequency.

    Since none of my MACs is able to perform AutoNegociation, I was trying to set the bridge to work in gigabit mode by writing its registers through MDIO. It seems (to me) that RX_CLK can’t be set that way and remain at its default value, as long as AutoNeg is not complete (which can’t be done)

    Here is my questions :

    -       Is it possible to set the DP83869 to work as a bridge RGMII / SGMII 1Gbps WITHOUT ANY AutoNegociation Process ?

    -       What is the configuration to do so (strapping/registers)?

    BR,

    Julien

  • Hi,

    I finally suceeded to use the component as RGMII to SGMII BRIDGE without any auto-negociation process.

    The configuration is the following:

    REG(0x170) = 0x8 << 8 # Activation of CLK_OUT at 125MHz

    REG(0xC6) = 0x10 # CLK-OUT control register (PLLCTL)

    REG(0xC00) = 0x0140 # BIT 12 = '0' = autoneg diseable

    In our case, it's important to active the bridge before the mac RGMII and SGMII.

    Thanks you,

    BR,

    Julien