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DS125DF1610: General Questions About Use As PRBS Generator

Sean Suttie
Intellectual 265 points
Part Number: DS125DF1610

Hi TI Support,

I had a general question about the DS125DF1610's PRBS Generator.

Is it possible to use the following ASIC only for the PRBS Generator? I am presently exploring this as a potential option to use on a test board that is intended to output PRBS patterns across a 10.315 G interface. Can the device be used only as a PRBS Generator without inputs on the RX pins?

Thanks,

Sean Suttie.

  • 0
    TI__Mastermind 19235 points

    Hi,

    Related to: "Can the device be used only as a PRBS Generator without inputs on the RX pins"

    • No, we require that some reference signal be present at the high-speed input of the channel in question.
    • This reference signal may be a simple 1010 clock pattern of sub-rate frequency of the full rate. The sub-rate clock signal divide by ratio may be as high a divide by 16.

    Cordially,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Intellectual 265 points

    Hi Rodrigo,

    Thank you for your quick and informative response.

    Out of interest do you know of any device/product that TI offers which acts mainly/only as a PRBS generator rather than a retimer which has it as a auxilliary feature?

    Thanks again,

    Sean Suttie.

  • 0 in reply to Sean Suttie
    Prodigy 50 points

    good evening

    if we can supply a clcok o the input pins take it that 644.53125Mhz would give us a recovered clock to PRBS to generate at 10.3G ?

    If so what jitter spec should we have on the clcok on the input pins

    what is the lowest Line rate we can acheive with this part,

    we are also looking to try and support 9G and 6G

    Davey

  • 0 in reply to david surphlis
    TI__Mastermind 19235 points

    Hi,

    We do not have a strict requirement for input jitter for the test case of PRBS generator with sub-rate clock input signal to the retimer high-speed input. As a guidance the output jitter for the sub-rate reference clock signal should be within the input jitter tolerance limits set for in the networking standards for 10.3125Gbps physical interfaces such as Ethernet 10G-KR and SFF8431 SFI interface. Though the PRBS generation in this mode decouples the output data from the input data, input jitter that is within the CDR bandwidth would affect it and transfer to the output.

    The SFF-8431 document may be accessed via link below. Refer to Table 14 and figures 20 and 21.

    https://www.fluxlight.com/content/Tech-Docs/SFPPlus%20MSA.PDF

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer