DS125DF1610: PRBS Pattern Generator Output w/o Input

Hi John,

Without an input source to provide a stable and known input frequency the 2nd DS125DF1610 will never be able to lock.  The lack of an input data stream means the transmitting DF1610 would have a free running VCO, the accuracy and consistency of this VCO in free running mode are not enough for the receiving DF1610 to achieve and maintain "lock".

Regards,

Lee

Hi Lee,

The RX CDR's ability to achieve and maintain "lock" not withstanding, I am unable to get a PRBS data stream out of the TX CDR.  Any suggestions on how I may have the TX device misconfigured?

The PRBS_DATA_CNT Registers are incrementing though I'm not seeing any output from the TX device.

I previously posted the register settings of one of the TX channel registers.

Below is a diagram of what I'm trying to achieve.

Hi John. Can you confirm that you are providing a valid input signal at the input of the DS125DF1610 channel under test, and then configuring the CDR rate on this channel accordingly (vie either channel register 0x2F or channel registers 0x60 to 0x64) to enable its CDR lock? Otherwise, you will not be able to have the retimer generate a PRBS stream..

Cordially,

Rodrigo Natal

HSSC Applications Engineer

Hi Rodrigo,
I am trying to generate the PRBS without an input. I'm trying to do some preliminary testing on the transmission lines while waiting for the proper test equipment that will generate 10G Ethernet. I've configured channel register 0x2F = 0xB6 for 10GE, 1GE and have forced a CDR Lock by setting the CDR_LOCK_OV and CDR_LOCK in channel register 0x0A(1,0). I've also forced a Signal Detect by setting bit 7 of channel register 0x14. I have also tried setting the LOW_POWER_MODE_DISABLE in channel register 0x34.

Is there no way to get the pattern generator to run off the internal free running VCXO?

You may try to run in free VCO running mode, however we cannot guaratee the resulting frequency when doing this and we do not recommend it for real applications.

You may experiment with the DS1xxDF1610 freeVCO run chaneel registers configuration routine below:

Type      REG        Value    Mask     Comment

RAW      14           80           80           //Force signal detect high

RAW      36           00           30           //referenceless all cap DAC

RAW      09           08           08           //enable bit to override pd_fd_cp and pd_pd_cp

RAW      18           00           01           //

RAW      92           01           03           //

RAW      09           08           08           //enable bit to override pd_fd_cp and pd_pd_cp

RAW      1B           00           02           //set CP_EN_CP_PD to 0

RAW      93           40           C0           //

RAW      09           80           80           //enable bit to override cap_cnt

RAW      08           08           1F           //set VCO cap DAC 0 to 8

RAW      77           00           20           // CDR_cap_dac_start0 to 0

RAW      09           40           40           //enable bit to ooverride lpf_dac_val

RAW      1F           15           1F           //

RAW      09           04           04           //enable bit to override divsel

RAW      18           00           70           //sel_div

RAW      0A           03           03           //cdr lock signal override

RAW      09           20           20           //bypass pfd

RAW      1E           80           E0           //pattern gen mode

RAW      1E           10           10           //enable serializer

RAW      79           20           60           // enable the pattern gen

RAW      30           09           0F           //enables clk for prbs gen, prbs9

Hi Rodrigo,

I have tried the register settings you provided but I still get no output out of the CDR.  I noticed in the steps you provided you wrote to Register 0x09 several times after various other register configurations.  Are there other procedural steps that I should be taking that I may be short cutting?  For example, placing the CDR in Reset prior to configuring the registers and then releasing the CDR from reset, [Ch Reg 0x0A(3,2)]?

Also, there were two RESERVED registers, 0x92 and 0x93 that you had me change.  There are no bit definitions for these two registers.  Just making sure that we're supposed to be accessing these registers or perhaps they are defined in another datasheet.  We are talking about the DS125DF1610 right?

In another post regarding this device, it was suggested that turning off the Single-Bit Transition checks.  Though since we are free-running I don't expect this to be an issue.  Link to other post below

https://e2e.ti.com/support/interface/high_speed_interface/f/138/t/472201?jktype=e2e

Thanks for your help

John

Hi John,

The write sequence is very specific.  Each register write comes with a "Data Mask" column.  For example if the mask is set to 0x80, then only bit[7] should be updated, the rest should stay as previously programmed (or default if not previously programmed).

Regards,

Lee