DS90UB960-Q1: REFCLK pin's voltage logic level

Hi,

     I have some doubts on REFCLK pin's voltage level.

 (1) In DS90UB960 EVM reference design, a 25MHz XO with 1.8V supply is used to source REFCLK pin, and DS90UB960's VDDIO is 3.3V.

 (2) In DS90UB960 datasheet, REFCLK pi's maximum amplitude is limited by VDDIO.

    My questions are below:

(1)What's  the power domain of REFCLK pin? VDDIO?

(2) Is it better to use a 25MHz XO with VDDIO supply?

for XO output is VDDIO voltage logic level and REFCLK input is also VDDIO logic level,the duty cycle is nearly same.

if the 25MHz XO is 1.8V powered and REFCLK is 3.3V LVCMOS level input, this may introduce some extra deviation to the duty cycle seen by REFCLK pin?