This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867IR: 100M Link Down, Conditions for link down

Part Number: DP83867IR

Hi team,

With a link up with a link partner at a media speed of 100M Full Duplex, our board links down once every few hours. The link partner side does not link down.

As a result of evaluation with 3 measuring instruments and 1 personal computer, 2 measuring instruments (same model) will be linked down.

The difference between link down and not link down is the content of bit [12: 8] in register 0x002D.

① Link down
0x002D [12: 8] = {0,0,01,1,0}
Enable FLD (0x002D, bit [15] = 1) in this state, link down immediately


② Not Link down:
0x002D [12: 8] = {0,0,01,1,0}
In this state, Enable FLD (0x002D, bit [15] = 1), no link down


Question 1: Conditions for detecting and canceling Bit10 (MLT3 Error)
Question 2: Conditions for detecting and canceling Bit9 (SNR level)
Question 3: Conditions for link down in the normal state (0x002D bit15 = 0)
 A) Does the link down condition differ depending on FLD on / off?
 B) The conditions are the same, but the threshold is different?
   C) etc.

//

Thank yo.

Best Regards,

Ryo Kukita