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DP83867IR: Ethernet link down

Part Number: DP83867IR

Hi Team, we would like to seek assistance, on a temperature of about 65°C or more, measured on the top,

There is a link down of ethernet communications (Gbit) and termination of MII serial messages. Supply voltages and 25MHz clock are ok. The skew programmed (RX and TX) was 1.5 or 2ns.

We would like to know if you are encountering a similar problem?

Thank you in advance.

Regards,

Mark 

  • Hi Mark,

    Was link working before and it suddenly drops? Or is the device not able to link at all around 65C? 

    Can you observe FLPs on the MDI pins at this temperature?

    Thank you,

    Nikhil

  • Hi Nikhil,

    Regarding the customer inquiry above of Mark, here's the information shared to us by the customer:

    Ethernet link works normally; when temperature exceeds a given threshold the link is lost.
     
    Here enclosed you will find some logic analyzer waveforms:
     
    1.
    top:    MDI communications, at time 1148.9 (about) communications ends
    bottom: particular at 1148.9, two attempts to communicate
     
    2
    top:    a normal message, with a DP83867 reply
    bottom: last message: no reply from DP83867, Data = FFFF

    Looking forward to your comment in the provided information above.

    Regards,

    Jonathan
  • Hi Jonathan,

    Thanks for the information. I have the following questions:

    1. Does the device come back on its own when the temperature is lowered? Or does it need to be reset?

    2. What is the clock source (crystal, external generator, etc.)? How is the 25MHz clock being monitored at high temp?

    3. Are the FLPs on the TD pairs still active when the device drops link?

    Thank you,

    Nikhil

  • Hi Nikhil, 

    At startup we observe flp signals over the A and B pairs.
    After link down there are also flp signals in A an B, but
    coming from the connected PC (we see them only if there
    is the cable).

    Communications does not come back.
    The processor (ultrascale +) uses a linux driver that stops
    the activity at link down, no reset or restart provided.

    The 25MHz clock signal is generated by a crystal.
    We observe it with an oscilloscope in XO: 0.94V average,
    2.0Vpp.
    During temperature test, in order to avoid a load, we
    connected the oscilloscope probe only capacitively to XO
    (about 200mVpp observed at the scope): clock signal never
    ceased.

    Thank you in advance for your input.

    Regards,

    Mark

  • Hi Mark,

    Responding to the first point about FLPs, I understand it seems as if the PHY is not sending FLPs after link down. Is this after the temperature is reduced back to below 65 C? Does the PHY recover on its own after the temperature is brought below 65 C, or does the PHY need a manual reset to become functional again.

    Instead of probing XO, can you probe the CLK_OUT pin? The 25 MHz clock should be observed on this pin as well. 

    Additionally, are you able to provide a schematic?

    Thank you,

    Nikhil

  • Hi all

    Finally we identify the cause of the failure.

    There is in our circuit a small resistor-transistor-logic connected to a pin

    (Xilinx logic port, 1.8V), provided to the processor for the reset of the chip

    (logically added to POR reset and system reset).

    This function is not used by software and the logic pin remained undefined.

    We expected a pin in tri-state; instead it operates a weak pull up, that at high

    temperature is enough to generate a reset of the chip.

    Many thanks to all for your support.

    Pietro Grazia,

    Neos srl 

  • Hello,

    I am glad to hear the system is no working! I will now close this thread.

    Thank you,

    Nikhil