TMDS181: TMDS181: No signal output when configured via i2c mode

Hi,

There are couple issues I see in the schematic.

1. SDA_SRC and SCL_SRC need to be pulled to ground if not used

2. SDA_SNK and SCL_SNK need to be connected to the DDC bus between the FPGA and the HDMI connector so the TMDS181 can snoop the DDC bus and correctly set the TMDS_CLK_RATIO_STATUS bit

3. Are you connecting the HPD signal from the HDMI connector to the FPGA?

4. How does the OE pin being controlled? The OE pin has an internal pullup so it only needs an external pulldown capacitor. We recommend a 0.22uF cap on the OE pin to make sure the power up timing requirement can be met

In the register dump, I see the TMDS_CLK_RATIO_STATUS being set to 1. TMDS_CLK_RATIO_STATUS only sets to 1 for HDMI2.0, it needs to be set to 0 for HDMI1.4 or lower operating speed.

Thanks

David

Hi,

1. In the register dump, I see the TMDS_CLK_RATIO_STATUS being set to 1. TMDS_CLK_RATIO_STATUS only sets to 1 for HDMI2.0, it needs to be set to 0 for HDMI1.4 or lower operating speed. Are you setting the TMDS_CLK_RATIO_STATUS bit correctly between the HDM1.4 and 2.0?

2. Are you setting the TX_TEMR_SEL bits correctly between the HDMI1.4 and 2.0?

Data rate (DR) > 3.4 Gbps – 75 to 150 Ω differential near end termination -> HDMI2.0

2 Gbps > DR < 3.4 Gbps – 150 to 300 Ω differential near end termination -> HDMI1.4

DR < 2 Gbps – no termination -> HDMI1.4

3. Can you probe the source card TMDS181 clock output when the TMDS181 is in I2C mode?

Thanks
David

Hi，David

1、I've tried to set the TMDS_CLK_RATIO_STATUS for HDMI1.4，but still link down；

2、The TX_TEMR_SEL bits of  the register has been seted to 01 for HDMI1.4，but still link down；

3、FPGA of INPUT CARD detected a clock signal in I2C mode。

Do you have anyother idea to analyse and  solve the problem?   or  Are there any other problems with my hardware circuit design？

How to configure the hardware circuit of  TMDS181 If the Output Card  can linkup at 4k@60hz via PIN starp mode?   and  How to configure the hardware circuit of  TMDS181 If the HDMI can display  between 1080P、4k@30hz and 4k @60hz？

GT status
---------
RX reference clock frequency: 148498432 Hz
DRU reference clock frequency: 125000000 Hz
RX: CPLL
RX state: ready

CPLL settings
-------------
M : 1 - N1 : 5 - N2 : 4 - D : 4

RX MMCM settings
-------------
Mult : 8 - Div : 1 - Clk0Div : 16 - Clk1Div : 8 - Clk2Div : 16

0x0 0x54
0x1 0x4d
0x2 0x44
0x3 0x53
0x4 0x31
0x5 0x38
0x6 0x31
0x7 0x20
0x8 0x1
0x9 0x2
0xa 0x33
0xb 0x8
0xc 0x60
0xd 0x0
0xe 0x0
0xf 0xf
0x10 0x0
0x11 0x0
0x12 0x0
0x13 0x0
0x14 0x0
0x15 0x0
0x16 0x0
0x17 0x30
0x18 0x0
0x19 0x0
0x1a 0x0
0x1b 0x0
0x1c 0x0
0x1d 0x0
0x1e 0x0
0x1f 0x0
0x20 0xa
0x21 0x0
0x22 0x0
0x23 0x0
0x24 0x0
0x25 0x0
0x26 0x0
0x27 0x0
0x28 0x0
0x29 0x0
0x2a 0x0
0x2b 0x0
0x2c 0x0
0x2d 0x0
0x2e 0x0
0x2f 0x0
0x30 0x0
0x31 0x0
0x32 0x0
0x33 0x0
0x34 0x0
0x35 0x0
0x36 0x0
0x37 0x0
0x38 0x0
0x39 0x0
0x3a 0x0
0x3b 0x0
0x3c 0x0
0x3d 0x0
0x3e 0x0
0x3f 0x0
0x40 0x0
0x41 0x0
0x42 0x0
0x43 0x0
0x44 0x0
0x45 0x0
0x46 0x0
0x47 0x0
0x48 0x0
0x49 0x0
0x4a 0x0
0x4b 0x0
0x4c 0x0
0x4d 0x0
0x4e 0x0
0x4f 0x0
0x50 0x0
0x51 0x0
0x52 0x0
0x53 0x0
0x54 0x0
0x55 0x0
0x56 0x0
0x57 0x0
0x58 0x0
0x59 0x0
0x5a 0x0
0x5b 0x0
0x5c 0x0
0x5d 0x0
0x5e 0x0
0x5f 0x0
0x60 0x0
0x61 0x0
0x62 0x0
0x63 0x0
0x64 0x0
0x65 0x0
0x66 0x0
0x67 0x0
0x68 0x0
0x69 0x0
0x6a 0x0
0x6b 0x0
0x6c 0x0
0x6d 0x0
0x6e 0x0
0x6f 0x0
0x70 0x0
0x71 0x0
0x72 0x0
0x73 0x0
0x74 0x0
0x75 0x0
0x76 0x0
0x77 0x0
0x78 0x0
0x79 0x0
0x7a 0x0
0x7b 0x0
0x7c 0x0
0x7d 0x0
0x7e 0x0
0x7f 0x0
0x80 0x0
0x81 0x0
0x82 0x0
0x83 0x0
0x84 0x0
0x85 0x0
0x86 0x0
0x87 0x0
0x88 0x0
0x89 0x0
0x8a 0x0
0x8b 0x0
0x8c 0x0
0x8d 0x0
0x8e 0x0
0x8f 0x0
0x90 0x0
0x91 0x0
0x92 0x0
0x93 0x0
0x94 0x0
0x95 0x0
0x96 0x0
0x97 0x0
0x98 0x0
0x99 0x0
0x9a 0x0
0x9b 0x0
0x9c 0x0
0x9d 0x0
0x9e 0x0
0x9f 0x0
0xa0 0x0
0xa1 0x0
0xa2 0x0
0xa3 0x0
0xa4 0x0
0xa5 0x0
0xa6 0x0
0xa7 0x0
0xa8 0x0
0xa9 0x0
0xaa 0x0
0xab 0x0
0xac 0x0
0xad 0x0
0xae 0x0
0xaf 0x0
0xb0 0x0
0xb1 0x0
0xb2 0x0
0xb3 0x0
0xb4 0x0
0xb5 0x0
0xb6 0x0
0xb7 0x0
0xb8 0x0
0xb9 0x0
0xba 0x0
0xbb 0x0
0xbc 0x0
0xbd 0x0
0xbe 0x0
0xbf 0x0
0xc0 0x0
0xc1 0x0
0xc2 0x0
0xc3 0x0
0xc4 0x0
0xc5 0x0
0xc6 0x0
0xc7 0x0
0xc8 0x0
0xc9 0x0
0xca 0x0
0xcb 0x0
0xcc 0x0
0xcd 0x0
0xce 0x0
0xcf 0x0
0xd0 0x0
0xd1 0x0
0xd2 0x0
0xd3 0x0
0xd4 0x0
0xd5 0x0
0xd6 0x0
0xd7 0x0
0xd8 0x0
0xd9 0x0
0xda 0x0
0xdb 0x0
0xdc 0x0
0xdd 0x0
0xde 0x0
0xdf 0x0
0xe0 0x0
0xe1 0x0
0xe2 0x0
0xe3 0x0
0xe4 0x0
0xe5 0x0
0xe6 0x0
0xe7 0x0
0xe8 0x0
0xe9 0x0
0xea 0x0
0xeb 0x0
0xec 0x0
0xed 0x0
0xee 0x0
0xef 0x0
0xf0 0x0
0xf1 0x0
0xf2 0x0
0xf3 0x0
0xf4 0x0
0xf5 0x0
0xf6 0x0
0xf7 0x0
0xf8 0x0
0xf9 0x0
0xfa 0x0
0xfb 0x0
0xfc 0x0
0xfd 0x0
0xfe 0x0
0xff 0x0
[END]
~ # 

Hi,

On the source side, if you only set the I2C_EN pin to high, leave TERM = NC, and don't do any I2C read or write, are you able to get the link up?

Please follow the design example in Figure 36, the key is to make sure the TMDS181 SDA_SNK and SCL_SNK connected to the DDC bus so the TMDS181 can snoop the bus correctly and set the TMDS_CLK_RATIO_STATUS bit correctly between the1080p, 4k@30, and 4k@60. The TX_TERM_SEL needs to be set to NC so it can automatically set to the right termination based on the data rate.

Thanks
David

Hi，David

  Thanks for your reply in these days？

  I found out the cause of the problem that CPU  don't configure  the register bit of video source of FPGA .Now the project can display to1080p  and 4k@60hz.  SDA_SNK and SCL_SNK need to be connected to the DDC bus between the FPGA and the HDMI connector .

I have anyother questions that need your reply？

1、how to configure PIN 17 ( SIG_EN) of TMDS181 IN PIN strap mode and i2c mode？ 

2、Does TMDS181  need to  pull up 50 Ω termination resistor  in DC-coupled mode （sink side  or source side）？

Hi,

Thanks for the update.

1. I would leave SIG_EN pin pulled low to disable the clock detector circuit in the pin-strap mode. In the I2C mode, pin 17 is overwritten by register 0x09 bit 4 which is disabling the clock detector circuit by default.

2. I think you are referring to the TMDS181 output? For the TMDS181 output and DC coupled mode, then there is no need to have the external 50ohm termination to 3.3v as long as the sink already internally has the termination.

Thanks

David