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TMDS181: TMDS181: No signal output when configured via i2c mode

WANG
Prodigy 90 points
Part Number: TMDS181

Hi ,all,

Using TMDS181RGZT and TPD12S016RKTR to build the HDMI signal channel between FPGA and display (FPGA is the sending end and the display is the receiving end).

The current problem is: HDMI don't output to 4K or 1080P via i2c mode ,but HDMI signal can display via pin strap mode.

Do you have any suggestion why TMDS181 don't have output via I2C mode?

7776.I2C register dump.TXT0312.TMDS181-OUTPUT-SCH.pdf

  • 0
    TI__Guru**** 167206 points

    Hi,

    There are couple issues I see in the schematic.

    1. SDA_SRC and SCL_SRC need to be pulled to ground if not used

    2. SDA_SNK and SCL_SNK need to be connected to the DDC bus between the FPGA and the HDMI connector so the TMDS181 can snoop the DDC bus and correctly set the TMDS_CLK_RATIO_STATUS bit

    3. Are you connecting the HPD signal from the HDMI connector to the FPGA?

    4. How does the OE pin being controlled? The OE pin has an internal pullup so it only needs an external pulldown capacitor. We recommend a 0.22uF cap on the OE pin to make sure the power up timing requirement can be met

    In the register dump, I see the TMDS_CLK_RATIO_STATUS being set to 1. TMDS_CLK_RATIO_STATUS only sets to 1 for HDMI2.0, it needs to be set to 0 for HDMI1.4 or lower operating speed.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 90 points

    Hi，David

     Thank you for your reply！

    1、SDA_SRC and SCL_SRC  have been pulled to groud；

    2、SDA_SNK and SCL_SNK have been connected to he HDMI connector,but still link down；

    3、The HPD signal  has connect from the HDMI connector to the FPGA，because HMDI can link up via pin strap mode for 1080P or 4k@30hz，

    4、OE pin connect to cpld，so OE pin pull high 30ms after power on；

    • This project consists of two board cards.A piece of the board use a piece of TMDS181 and FPGA for HMDI Source,Another

      board use a piece of TMDS181 and FPGA for HMDI Sink。

    • If the source card and sink card configure via pin strap mode，they can be linked up in 1080P or 4k@30hz。However，the source card configures via I2C
    • mode，and the sink card still configures via pin strap mode，they can't link up.
    • Do you have any suggestion why TMDS181 don't have output via I2C mode?

    Block Diagram of TMDS181.pdfTMDS181-SOURCE.pdfTMDS181-SINK.pdf

  • 0 in reply to WANG
    TI__Guru**** 167206 points

    Hi,

    1. In the register dump, I see the TMDS_CLK_RATIO_STATUS being set to 1. TMDS_CLK_RATIO_STATUS only sets to 1 for HDMI2.0, it needs to be set to 0 for HDMI1.4 or lower operating speed. Are you setting the TMDS_CLK_RATIO_STATUS bit correctly between the HDM1.4 and 2.0?

    2. Are you setting the TX_TEMR_SEL bits correctly between the HDMI1.4 and 2.0?

    Data rate (DR) > 3.4 Gbps – 75 to 150 Ω differential near end termination -> HDMI2.0

    2 Gbps > DR < 3.4 Gbps – 150 to 300 Ω differential near end termination -> HDMI1.4

    DR < 2 Gbps – no termination -> HDMI1.4

    3. Can you probe the source card TMDS181 clock output when the TMDS181 is in I2C mode?

    Thanks
    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 90 points

    Hi，David

    1、I've tried to set the TMDS_CLK_RATIO_STATUS for HDMI1.4，but still link down；

    2、The TX_TEMR_SEL bits of  the register has been seted to 01 for HDMI1.4，but still link down；

    3、FPGA of INPUT CARD detected a clock signal in I2C mode。

    Do you have anyother idea to analyse and  solve the problem?   or  Are there any other problems with my hardware circuit design？

    How to configure the hardware circuit of  TMDS181 If the Output Card  can linkup at 4k@60hz via PIN starp mode?   and  How to configure the hardware circuit of  TMDS181 If the HDMI can display  between 1080P、4k@30hz and 4k @60hz？

    TMDS CLOCK.txt
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    GT status
    ---------
    RX reference clock frequency: 148498432 Hz
    DRU reference clock frequency: 125000000 Hz
    RX: CPLL
    RX state: ready
    CPLL settings
    -------------
    M : 1 - N1 : 5 - N2 : 4 - D : 4
    RX MMCM settings
    -------------
    Mult : 8 - Div : 1 - Clk0Div : 16 - Clk1Div : 8 - Clk2Div : 16
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    TX_TEMR_SEL(150-300ohm).txt
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    0x0 0x54
    0x1 0x4d
    0x2 0x44
    0x3 0x53
    0x4 0x31
    0x5 0x38
    0x6 0x31
    0x7 0x20
    0x8 0x1
    0x9 0x2
    0xa 0x33
    0xb 0x8
    0xc 0x60
    0xd 0x0
    0xe 0x0
    0xf 0xf
    0x10 0x0
    0x11 0x0
    0x12 0x0
    0x13 0x0
    0x14 0x0
    0x15 0x0
    0x16 0x0
    0x17 0x30
    0x18 0x0
    0x19 0x0
    0x1a 0x0
    0x1b 0x0
    0x1c 0x0
    0x1d 0x0
    0x1e 0x0
    0x1f 0x0
    0x20 0xa
    0x21 0x0
    0x22 0x0
    0x23 0x0
    0x24 0x0
    0x25 0x0
    0x26 0x0
    0x27 0x0
    0x28 0x0
    0x29 0x0
    0x2a 0x0
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    0x2c 0x0
    0x2d 0x0
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    0x32 0x0
    0x33 0x0
    0x34 0x0
    0x35 0x0
    0x36 0x0
    0x37 0x0
    0x38 0x0
    0x39 0x0
    0x3a 0x0
    0x3b 0x0
    0x3c 0x0
    0x3d 0x0
    0x3e 0x0
    0x3f 0x0
    0x40 0x0
    0x41 0x0
    0x42 0x0
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to WANG
    TI__Guru**** 167206 points

    Hi,

    On the source side, if you only set the I2C_EN pin to high, leave TERM = NC, and don't do any I2C read or write, are you able to get the link up?

    Please follow the design example in Figure 36, the key is to make sure the TMDS181 SDA_SNK and SCL_SNK connected to the DDC bus so the TMDS181 can snoop the bus correctly and set the TMDS_CLK_RATIO_STATUS bit correctly between the1080p, 4k@30, and 4k@60. The TX_TERM_SEL needs to be set to NC so it can automatically set to the right termination based on the data rate.

    Thanks
    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 90 points

    Hi，David

      Thanks for your reply in these days？

      I found out the cause of the problem that CPU  don't configure  the register bit of video source of FPGA .Now the project can display to1080p  and 4k@60hz.  SDA_SNK and SCL_SNK need to be connected to the DDC bus between the FPGA and the HDMI connector .

    I have anyother questions that need your reply？

    1、how to configure PIN 17 ( SIG_EN) of TMDS181 IN PIN strap mode and i2c mode？ 

    2、Does TMDS181  need to  pull up 50 Ω termination resistor  in DC-coupled mode （sink side  or source side）？

  • 0 in reply to WANG
    TI__Guru**** 167206 points

    Hi,

    Thanks for the update.

    1. I would leave SIG_EN pin pulled low to disable the clock detector circuit in the pin-strap mode. In the I2C mode, pin 17 is overwritten by register 0x09 bit 4 which is disabling the clock detector circuit by default.

    2. I think you are referring to the TMDS181 output? For the TMDS181 output and DC coupled mode, then there is no need to have the external 50ohm termination to 3.3v as long as the sink already internally has the termination.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 90 points

    Hi，David

      Thank you for your help in these days !