DS90UB953A-Q1: MIPI Interface of DS90UB953A

hi, pls check below comments.

 Q1) CSI errors were only observed on Pattern③　 (Sensor :Non-Continuous clock setting /953A :Continuous clock setting ) .
　　954　addr0x4E　（RX_PORT_STS2 ）　Read data:　0x4D　（CSI_ERROR=1）
　　954　addr0x7A　（CSI_RX_STS ）　　   Read data:　0x02    （ECC2_ERR=1）

  But after a few ms the CIS error disappears. Does it have the function to recover from CSI errors on 953A-954 system?
TI: no, 954 can't recover the CSI2 error! for your issue, it sounds the FPD-Link has many errors, pls resolve it as this would impact the CSI2 error.

anyway the clock mode setting of CSI2 is not correct! pls make them align. this test doesn't make sense!

Q2)  CSI errors could not observed on  Pattern②　 (Sensor :Continuous clock setting /953A :Non-Continuous clock setting ) .
The behavior  is the same as Pattern ①   (Sensor :Continuous clock setting /953A :Continuous clock setting ) .
Why doesn't errors occur even though the clock mode settings are different between the sensor and 953A?

TI: the clock mode setting of CSI2 is not correct! pls make them align. this test doesn't make sense since this setting is not correct.

Q3) The following alarm will be obseved to the addresses 4D and 4E of 954 after the initial setting.
　　954　addr0x4E　（RX_PORT_STS2 ）    Read data:　0x45    （LINE_LEN_CHG=1/LINE_CNT_CHG=1）
Let me check if the behavior is correct.

TI: the link has bit error, pls make sure the link channel has good si performance, such as connector / cable s parameter, impedance, layout, poc layout and design, etc.

regards, Steven

Hi, Steven san

Thank you for your quick reply.
But Did you confirm the attached file?

(1) We know MIPI clock setting is wrong. However, the sensor output is displayed correctly.
Let me know its reason.

(2) Same as (1) Please check my report.

(3)    954　addr0x4E　（RX_PORT_STS2 ）    Read data:　0x45    （LINE_LEN_CHG=1/LINE_CNT_CHG=1） after Power ON
　　　　　　　　　　　　　　　　　　　　　　　　　　　　↓　a few milli seconds later
                                                                                                   0x04 （ LINE_LEN_CHG=0/LINE_CNT_CHG=0）

Is this result a bit error?

Hello,

1. if the clocking mode (continuous vs non-continuous) are not aligned between sink and source, it could  make the link unstable. we have some lesson learnings here, the cause is that the DPHY inside module needs detect and switch the HS and LPS based on different design, it could make the logic design un-stable if the mode is not aligned.

2. I had checked the attached, but can't understand it well. for example, what is the column I (2bytes data?) but anyway, please make sure:

a. the conti. / non-conti clock mode should be aligned. ti also only validated the clock mode alignment cases

b. if the clock mode is aligned, the link still has issue, please dig out if the issue is from the link between sensor and 953 or from the fpd-link between 953 and 954, or from the link between 954 and its sink? 

c. to check if the issue is from the 953 and 954, you can check reg. 0x4c/4d/4e/55/56/73/74/75/76 etc

3. generally, you can check reg. 0x4d/4e NOT check line length change directly. the endec error or parity error could result into length change as well but they are fully same. typically bit error is more easily reported than length change.

also, to check CSI2 error, you can check fpd-link error firstly. if the fpd-link has no error but csi2 reg. has error, it could be the error is from the i/f between sensor and 953.

best regards,

Steven

Thank you for your reply.

1),2)
I understood. thank you.

３）
What is the endec error?
but I understood that if the LINE length / Count of addresses 4D and 4E only changes, it can be judged that it is not an error.
If error(FPD or CIS2)  is occor, we recoginized that we  have to check 0x4c/4d/4e/55/56/73/74/75/76 etc.
best regards,

Hi,

the endec error means the internal coding error, this is another error detection combing with the parity error in the link.

generally, you should check 0x4d/4e/55/56 on the FPD-Link channel as we suppose this link is the most weak in the total system due to long reach transmission over cable.

if the FPD-Link has error, it could introduce the line length change and the CSI2 error. but if the FPD-Link has no error, the line length or CSI2 error could be from the i/f between sensor/isp and the serializer, the error at this port could be transmitted to the de-ser side.

regards,

Steven

Sorry,I still don't understand.
Is the endec error an encoder error (adrr0x4E, bit5)?

Best regards.