DS90UB954-Q1: 914's operation when releasing clock stretch of I2C

Yoshida-san,

The pictures/attachments did not get posted on the thread properly. Can you re-attach?

Hi Palaniappan-san,

Thank you for your support.

I attach the pictures as followed.

1. Assumed system configuration

2. Assumed Format To Remote I2C Slave

 This is the behavior when 914 releases the clock stretch as enclosed in red.

3. I2C transaction

I would like to know how 914 handles SCL, SDA in the part enclosed in red.

I believe that SDA will remain as long as host does not lower SCL to Low.

II want to know if 914A could pull SCl low or change SDA before the host pull SCL low.

In that case, I want to know under what conditions it will happen.

Best regards,

Tomoaki Yoshida

Hi Palaniappan-san,

I have an additional question.

Is SDA always high while 914 is pulling the SCL low for clock stretch?

I think that the waveform will be as follows.

Please tell me if there is any mistake in my perception.

Note: The content of the data has no particular meaning.

Best regards,

Tomoaki Yoshida

Hi Palaniappan-san,

Any update on this issue?
We need to confirm correct operation of 914A as soon as possible.
I look forward to hearing from you.

Best regards,
Tomoaki Yoshida

Hi Palaniappan-san,

In our customer's case, the host expects 914A to release the SDA that was pulled low with Ack after 914A releases the SCL.
But I understand that 914A will release the SDL after waiting for SCL's falling edge after releasing the SCL.
The SCL should be controlled by the master.

I would like to confirm how the 914A is correct and where in our recognition there is a mistake.

I'm sorry to bother you over and over.

Best regards,
Tomoaki Yoshida

Yoshida-san,
The 913A/914A supports clock stretching as per the I2C specification. From the datasheet:

To communicate and synchronize with remote devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low on the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock and only stretches it until the remote peripheral has responded. The I2C master must support clock stretching to operate with the DS90UB913A/914A chipset.

Please refer to the I2C specification section 3.1.9 for more details on clock stretching.

Hi Palaniappan-san,

Thank you for your support.

I am evaluating while looking at the specification sheet of I2C and the data sheet of 914A.

It was confirmed that the remote slave access was done correctly.

However, I have one point that I do not know whether it meets specification, so please tell me your opinion.

Monitor the  Host (914A side) I2C and Remote (913A side) I2C like the waveform below.

The point to worry is that SDA is Low or High while remote SCL is stretched Low.

For Host I2C, SDA is High during clock stretch.

Under the I2C specification, I think that SDA will be released after returning ACK, is this correct behavior?

In the configuration described above, writing from the host to the register of the imager which is the remote slave.

I thought that the remote SDA will be High at this timing as shown in the previous figure, so I want to check if this is a correct behavior.

Best regards,

Tomoaki Yoshida

Hi Palaniappan-san,

Any update on this issue?

I look forward to your response.

Best regards,

Tomoaki Yoshida

Hi Palaniappan-san,

Thank you for your support.

I have been taught before, so I refer to the attached document.
However, I was not sure about SDA during the SCL Low period of remote I2C.
In addition, when checked on the evaluation board, both are present in the case of High and Low.
I thought that after the remote slave returned ACK, SDA was released and should be High.
Indeed, SDA is always high during the SCL Low period of host I2C.
Because both High and Low exist, I am also confused.

There is no particular problem, but I want to know if this is correct behavior.
If possible, can you tell me how High and Low are determined?

Best regards,
Tomoaki Yoshida

Yoshida-san,
The SDA can change to HIGH or LOW when the SCL is low and this is normal (the data on the SDA line must be stable when SCL is high).

You can refer to the I2C specification here for additional information:
www.nxp.com/.../UM10204.pdf