Other Parts Discussed in Thread: SN74LXC8T245
Hi
I use the SN74LVCH8T245 as a level shifter from my FPGA (1.8V) to my CPU (3.3V)
In the datasheet you wrote several times it is not recommended to use PullUp/ Down resistors
on the device inputs (this is correct for the device outputs as well??)
What is the cause for this request? It it because a "voltage divider" will appear between
the device internal resistors and the board external Pull Up/ Down resistors?
However, on section 10 you wrote that when pin OEn is always low (always active) it is
better to use Pull Up/ Down on the device inputs.... Why is that?
What is the bottom line, with or without external PU/ PD ??
In case my OEn pin is connected to the POR (Power On Reset) signal (POR is "1" for 250mS
from power up and afterwards it is constantly low), is it still comply with section 10
and I should connect my inputs to PU/ PD ? Please explain ...
Thanks
Amnon Pomerants