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Original question:

SN74LVC2G74-Q1: What is the sample timing of the input high/low

SN74LVC2G74-Q1: What is the outputs when the pin PRE and CLR is H, while CLK is H?

Matthew Chen
Intellectual 1140 points
Part Number: SN74LVC2G74-Q1

Hi team, 

What is the outputs when the pin PRE and CLR is H, while CLK is H?

I see other competitor device marked here as non low to high transition and ours marked as L. Are they the same? 

 

Matthew 

  • 0
    TI__Genius 14250 points

    Hi Mathew,

    The clock of this device is edge triggered -- ie it will not change anything if it's not a rising edge. This is indicated by the up arrows in the function table. The output at this condition will contain previous state. 

    Regards,

    Sebastian