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SN74LVC1G74: D-Type Flip-Flop /CLK issues in ESD test

Darren Wen
Prodigy 250 points
Part Number: SN74LVC1G74

Hi team,

We have a question about D-Type Flip-Flop /CLK issues in ESD test need your support.

SN74LVC1G74 is used in system, we find that /CLK will be affect and change to low when conduct ESD test, which lead to a wrong signal to output.

Do we have solutions for this problem?

If another suitable device can solve this problem, you can recommend it. Form my knowledge, may be add a delay time for response /CLK can solve this problem, please give your command. Thank you!

BR,

Darren  

  • 0
    Guru 261240 points

    You could add a low-pass filter in front of a Schmitt-trigger buffer.

    A better solution would be to prevent the ESD from influencing the clock line. Why does this happen? Is the clock signal exposed to the outside?

  • 0 in reply to Clemens Ladisch
    TI__Prodigy 250 points

    Hi Clemens,

    My mistake that the /CLK in question should be /CLR, clear input function and put low to set output low. In ESD test, we find that /CLR might be affect and change to low. 

    1. can you share how to add a low-pass filter solution in the circuit? below is the typical circuit.

    2. is there another device with low slew response to /CLR change or have a delay time? Maybe it is another ideas, can you share your comments?

    BR,

    Darren

  • 0 in reply to Darren Wen
    Guru 261240 points

    1. That example circuit delays the rising edge when VCC powers up. You can use the same principle (series resistor after the signal source, and capacitor to ground) to filter out short pulses on /CLK. But where does the /CLK signal come from? How is the ESD pulse coupled into this trace?

    2. All logic devices are designed to quickly react to changes at their inputs.