FAQ: Logic and Voltage Translation > Output Parameters >> Current FAQ
The maximum trace length that a logic device can drive is 60 mm. This is a safe trace length for most logic devices to drive across the majority of applications. This can often be pushed to 120 mm (4700 mil), however some logic devices may see signal integrity (SI) issues between these two values depending on the application.
The trace length that a logic gate can drive is heavily dependent on the physical and electrical characteristics of the trace and can be impacted by the type of logic used. Faster output state transitions generally result in more transmission line issues due to increased signal bandwidth.
60 mm is short enough that all logic devices can consider this a ‘lumped model’ circuit and won’t see any issues. Beyond that, the trace can begin to act like a transmission line, and signal bandwidth (based on the transition rate) will significantly affect signal integrity.
If properly matched, a transmission line can actually be extremely long without any problems, however this requires some careful system design. For more information on driving a long trace length, see this FAQ: [FAQ] What happens when I connect a logic device's output to a 50 ohm transmission line?
TI does offer some devices that are specifically designed to drive long traces. For example, the AUC logic family is designed to drive 1.8-V signals on 50-ohm transmission lines. This family has very fast transitions (typically under 1 ns), but the output design produces excellent signal integrity into 50-ohm controlled impedance transmission lines.
To see logic buffers in the AUC family, please follow this link: AUC Family non-inverting buffers & drivers
There are also multi-channel buffers designed to help with driving data busses across longer trace lengths. These devices include damping resistors to help match outputs to 50-ohm controlled impedance traces. For a pre-filtered list of these, please follow this link: Non-inverting logic buffers with output damping resistors
The 60 mm standard can be shown mathematically from the typical bandwidth of a logic device, 300 MHz, and the typical effective permittivity of a PCB εr, around 4. The phase velocity of the signal is calculated by v_ph=c/√(ε_r ). The wavelength of the signal is then λ=v_ph/BW. The signal may begin to experience SI issues with a trace more than 1/8th of the signal’s wavelength, λ/8=c/(8*BW*√(ε_r ))=((3*10^8 m/s))/(8*300*10^6 Hz*√4)=1/16 m=62.5 mm. We have rounded that down to our answer of 60 mm.
Finding the maximum safe trace length and protecting against SI issues is important in a wide array of applications where board design requires that a logic device drive a long trace. Anticipating and mitigating these issues using the formulas and devices discussed above is of particular importance in applications such as communication equipment, where component-dense boards may require logic devices to drive long traces at high frequencies.