hi,
The Q output is occasionally not kept low even after CLR is already set at low during power-up in which the CLK and CLR ramp up speed is very low (rise speed is 3.3v/2s). The detail test waveforms are attached.
there are 2 questions as below.
Questions:
- Are there any rise/fall rate requirement for both CLK and CLR of SN74LV273?
- About the issue listed in test report, is it caused by rise speed of CLK and CLR?
