SN74LVC1G125: simple single ended clock buffer cmos level shift

Bernd Jestädt

Part Number: SN74LVC1G125
Other Parts Discussed in Thread: SN74AUP1T34, SN74AXC1T45, , SN74AUP1T17

Dear TI Team,

we need a simple buffer / redriver for a 125MHz cmos clock to shift from 2.5V level to 3.3V.

Dedicated (zero delay) clock buffers always have more than one channel.

For simple signal buffers I am not sure about the jitter performance. The propagation delay is not limited, but should stay equal and balanced for rising and falling edge.

Dual voltage solutions would be the SN74AUP1T34 or the SN74AXC1T45.

Using a single voltage buffer would significantly simplify the layout / placing and if supplied with 3.3V Vih min is 2V.

Could we also use a simple SN74LVC1G125 ?

Thanks for your check and any suggestions.

best regards,

Bernd

10 months ago

0 Clemens Ladisch 10 months ago

Guru 243180 points

Yes, 2.5 V is high enough for LVC at 3.3 V. But the actual switching threshold is near V_CC/2, so the propagation delays for rising and falling edges will not be symmetrical. (There are single-supply devices with lowered input switching thresholds like the SN74AUP1T17, but there the threshold would be below the middle of a 2.5 V signal.)

0 Bernd Jestädt 10 months ago in reply to Clemens Ladisch

Prodigy 10 points

Thanks, Clemens. We will test with this buffer type and see if symmetry is ok for clock receiver.

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SN74LVC1G125: simple single ended clock buffer cmos level shift