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CD4093B-MIL: CD4093B-MIL

William Probasco
Prodigy 30 points
Part Number: CD4093B-MIL
Other Parts Discussed in Thread: CD4093B, TLV803E

I have configured an RS Filp-flop with two of the NAND gates in the CD4093B package.  When the power is applied, both inputs are biased up to Vcc (11.4V) through 100k resistors.  Using a scope, it appears that both of the inputs come up at the same time and the output is set to high.  However, I need to ensure that this will ALWAYS be the case, do I not?  How can I determine for certain which of the two outputs will be set to high?  I thought that if I delay the input of the gate who's output I want to go high initially I would be insured a proper start-up every time.  Am I correct?  Maybe I need take no action (this is doubtful)?  Thank you in advance.

  • 0
    TI__Genius 14200 points

    William,

    Could you draw a quick sketch of what sort of timing you're aiming for? Maybe a schematic as well? It's not immediately clear to me what the goal/issue is here.

    By "both inputs" do you mean the inputs of the NAND gates? And I'm assuming you mean one input for each gate (otherwise the output wouldn't be high)? I'm also confused by what you mean when you say "how can I determine which of the two outputs will be set to high". To me the answer would be that the output that goes high corresponds to the channel and set of inputs that you choose to use and that not any extra work is required here but I feel like I'm just misunderstanding what you are asking.

    Best,

    Malcolm

  • 0
    Guru 256410 points

    There is no guarantee. The only way to get a NAND-based latch into a known state is to pull one input low. Use a reset signal; if needed, generate it with an R-C circuit or a voltage supervisor like the TLV803E.