Other Parts Discussed in Thread: CD4093B, TLV803E
I have configured an RS Filp-flop with two of the NAND gates in the CD4093B package. When the power is applied, both inputs are biased up to Vcc (11.4V) through 100k resistors. Using a scope, it appears that both of the inputs come up at the same time and the output is set to high. However, I need to ensure that this will ALWAYS be the case, do I not? How can I determine for certain which of the two outputs will be set to high? I thought that if I delay the input of the gate who's output I want to go high initially I would be insured a proper start-up every time. Am I correct? Maybe I need take no action (this is doubtful)? Thank you in advance.