Hello,
I have read in the data sheet (chapter 7.3.9) that the internal resistors are static 71k. However, in the FAQ (https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1101096/faq-why-is-there-a-voltage-offset-at-the-input-of-the-sn74axcxtxxx-device) they are described as dynamic resistors. Which of the two is correct?
I have already made a few measurements on this chip with a pull-up potentiometer on a data line connected (line floating, input-side). My result there was that they are dynamic. As soon as I was below 33k pull-up (with VCC = 3V0), the corresponding line jumped to VCC.
Best Regards,
Yannick