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SN74AXC4T774: Internal pull-down resistors on the IOs: dynamic or static?

Part Number: SN74AXC4T774

Hello,

I have read in the data sheet (chapter 7.3.9) that the internal resistors are static 71k. However, in the FAQ (https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1101096/faq-why-is-there-a-voltage-offset-at-the-input-of-the-sn74axcxtxxx-device) they are described as dynamic resistors. Which of the two is correct?
I have already made a few measurements on this chip with a pull-up potentiometer on a data line connected (line floating, input-side). My result there was that they are dynamic. As soon as I was below 33k pull-up (with VCC = 3V0), the corresponding line jumped to VCC.

Best Regards,

Yannick

  • Hi Yannick,

    Static. Please further note that the data sheet mentions pull-up should be no larger than 7K to help avoid such contention, thanks. 

    Best Regards,

    Michael. 

  • Hi Michael,

    Thank you for your reply. However, I am noticing a slightly different behavior with my measurement. If they were static, then I would always have a voltage divider. However, my measurement has shown that from 0k to approx. 33k pull-up, the voltage level at the input is at the corresponding VCC level. Only with higher pull-up values does the voltage level "jump" to the value that would be expected with an internal 71k pull-down.

    Best Regards,

    Yannick

  • Hi Yannick,

    To clarify, do you mean the port is configured as input not output? I.e. Input port is pulled-down until pulled strongly high.
    Hence, if the port is configured as output, then pull-down will be active in disabled mode only until it is strongly pulled to high.

    It is a matter of when they are active or inactive (when port strongly driven to logic high). Please let me know if still unclear, thanks.

    Best Regards,

    Michael.