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SN54SC6T17-SEP: Figure 7-2, VIH(min) and VIL(max), Tabular Format Available?

Rob Weinstein
Prodigy 30 points
Part Number: SN54SC6T17-SEP

Hello,

This is my first post here.  I'm designing in the SN54SC6T17-SEP and I'm trying to calculate the DC level margins at the inputs to the device.  I'm used to a table showing VIH(min) and VIL(max) for a particular range of VDD.  The SN54SC6T17-SEP data sheet helpfully provides Figure 7-2 SCxT Input Voltage Levels.  As I understand it, VIH(min) is represented by the red dashed line and VIL(max) is represented by the black dashed line.  Does TI have a document with those two curves in tabular form or fitted equations in which I can enter VDD and temperature and get the VIH(min) and VIL(max) values?  Section 7.3.4 says "Figure 7-2 shows the typical VIH and VIL levels ..." Are these curves available across temperature?

For example, let's say I want to know VIH(min) and VIL(max) at different VDD values:

  • VDD = 4.75 and 5.25 V, Temp = -40 to +85 C
  • VDD = 3.15 and 3.45 V, Temp = -40 to +85 C
  • VDD = 2.45 and 2.55 V, Temp = -40 to +85 C

Thanks,

Rob

  • 0
    TI__Mastermind 25320 points

    Hi Rob,

    Welcome to E2E forum. 

    • VDD = 4.75 and 5.25 V, Temp = -40 to +85 C: VIH (min) = 1.121 V and VIL(max) = 1.029 V
    • VDD = 3.15 and 3.45 V, Temp = -40 to +85 C: VIH (min) = 0.86 V and VIL(max) = 0.809 V
    • VDD = 2.45 and 2.55 V, Temp = -40 to +85 C: VIH (min) = 0.725 V and VIL(max) = 0.71 V

    However, see section 5.5 with Vt+ max as VIH and Vt-min as VIL similar to the figure.

    Please note that this is different due to Schmitt Trigger inputs. Please see Understanding Schmitt Triggers further clarifying, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 30 points

    Hi Michael,

    I started out looking at Table 5.5 but my interpretation of it made me think that the SN54SC6T17 can't work, that's when I started looking at Figure 7-2.

    Thank you for providing the link to Understanding Schmitt Triggers.  After reading it, I'm even more convinced that it won't work, here's why:  In that App Brief, right under Figure 1, it says:

    In the figure above, the input levels Vih and Vil must
    be greater than (VT+ max) and less than (VT– min)
    to ensure the part will switch.

    With that in mind, my FPGA's LVCMOS25 output has a VOL(max)=0.4 V.  The App Brief says, " Vil must be ... less than (VT– min) to ensure the part will switch."  From SN54SC6T17 datasheet table 5.5, VT-(min) for 2.25 to 2.75 is 0.374 V.  So, the FPGA output at 0.4 V doesn't meet the condition specified by the App Brief.  That's kind of wordy, let me put it in a table:

    Device Parameter Value (V) Note
    FPGA LVCMOS 25 Output VOL(max) 0.4 FPGA's VOL is SN54SC6T17's VIL

    SN54SC6T17 (2.25 V to 2.75 V)

    		 VT-(min) 0.374

    App Brief says, "Vil must be ... less than (VT– min) to ensure the part will switch."

    0.4 V is NOT less than 0.374 V. It looks like we fail this.

    Am I reading this wrong?

    Thanks,

    Rob

  • 0 in reply to Rob Weinstein
    TI__Mastermind 25320 points

    Hi Rob,

    I see the confusion. It mainly means the lower the VIL the better i.e requiring lower switching consumption for the VOL.

    However, the device will switch for LOW for voltages lower than Vt-max 0.71V. Hence 0.4 V is okay, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 30 points

    Hi Michael,

    Your interpretation would make my life a lot easier because I'd be done now, unfortunately, I'm not convinced. I think the sentence you highlighted means that the device can switch in that region and, more importantly, can't switch in the no man's land region between those two bands. I suspect the height of those bands is likely dictated by voltage, temperature, and process variations. However, I think the very first sentence of that paragraph is a key point:

    "It is important to remember (Vt+ max) = Vih and (VT– min) = Vil."

    I discovered that Figure 1 in the App Brief is partially obscured by Figure 2. I opened it in Acrobat Reader, right clicked on Figure 1, copied the complete image, and pasted below:

    I noticed on the right side that there are little arrows pointing to the uppermost and lowermost lines with labels Vih and Vil, respectively. I think those previously-obscured details reinforce that first sentence about (Vt+ max) = Vih and (VT– min) = Vil.

    I remain unconvinced that the device is guaranteed to switch if the input falls within either of the VT+ or VT- bands. My interpretation is that switching is only guaranteed if the input is greater than Vih or less than Vil (because it says as much in the paragraph under Figure 1). I'm not sure where to go from here.

    Thanks,

    Rob

  • +1 in reply to Rob Weinstein
    Guru 258710 points

    Is is correct to consider the worst-case values in table 5.5; VT+(max) and VT−(min) are what matters.

    But the VOL/VOH values you are using are worse than your actual worst case. They are specified for a certain output current, but the actual output current will be much smaller when connect to a high-impedance CMOS input, so the actual output voltages will be near GND or VCC. (You can model CMOS outputs as resistors; see [FAQ] What is the output voltage (VOH or VOL) when the output current is X or the supply voltage is Y?)

  • 0 in reply to Clemens Ladisch
    Prodigy 30 points

    Hi Clemens,

    Thank you for confirming that my interpretation of the App Brief is valid.

    Your assertion that "the VOL/VOH values you are using are worse than your actual worst case" is very helpful. The FAQ you linked is exactly what I need to solve this problem. I plugged in some values from my FPGA and found that its Ron varies by drive strength from 100 ohms at 4 mA to 25 ohms at 16 mA. Then I found the input current, II, for the SN54SC6T17-SEP is 1 uA max. This gives a worst-case VOL of 100 uV. I'm convinced, this device will work just fine.

    Here's a snippet from my spreadsheet:

    Now I've got a new tool in my bag of tricks for performing DC analysis!

    Thanks,

    Rob