• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 18 subscribers
  • Views 1606 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Minimums for Logic families' rise and fall times on the clock pin

Gary Dowdy
Prodigy 50 points

What logic families are sensitive to slow rise and slow fall times?  I find that HC/HCT needs at least a 500ns rise/fall time in an old Signetics user's guide that I have.  Does TTL, 4000 series CMOS, and most newer CMOS technologies have specs for minimum rise/fall times?  The follow-up question is, is the slow rise or slow fall time on the clock destructive physically, stressing the part (overheating due to latch-up, metastable, linear region operation, etc), or is the spec there to maintain data integrity and predictability.  The system level question is, can I use a sinusoidal shaped clock signal for testing circuits prior to shipping?

  • 0
    TI__Guru 59460 points

    Hi Gary ,

    Most of the logic families have the recommended spec on the transition rate but schmitt trigger devices are built to handle slow signals like sinusoid on its input .

    There are issues with slow signals which are better explained in the app note attached . Usually , output oscillations , higher power consumption which can be damaging to the device in extreme cases .

    7510.slownfloatingCMOS_scba004c.pdf

  • 0
    Prodigy 50 points
    Thank you for this response. You are answering the question at the technical level that I need. I am seeing the destructive mechanisms in the shoot-through current, through current, when the stacked transistors are both on (partially on), creating a direct path, power to ground. A follow-up question --- The SCBA004C App Note/White Paper is specific to advanced CMOS (AC/ACT, AHC/AHCT, ALVC, CBT, CBTLV, HC/HCT, LVC, LV/LV-A) and BiCMOS (ABT, ALVT, BCT, FB, GTL, and LVT). What about 4000 series CMOS (CD4000)? If CMOS devices, in general, have a rise/fall time minimum in the datasheet, then I am covered for CMOS. The question I would have for 4000 series CMOS and TTL (54/74, LS, S) would be, what are the rise/fall times that one would design-in a Schmitt-trigger input. What rise and fall transitions, would I design in a 54/74LS14, 54/74S14, or CD40106? Another way to ask the question is --- is there a shoot-through scenario in the bipolar TTL architecture, and if so, what is the slew rate that I would be ok not being destructive to the device?
  • 0 in reply to Gary Dowdy
    TI__Guru 59460 points
    Hi Gary ,

    I am unsure of the transition rate for bipolar or CD4K parts unless mentioned in the datasheets .
    I would see similar devices in the same family if I can find one . Also , there are no requirements for transition rate for Schmitt trigger parts since they are required to handle slow , noisy signals .