I'm using the SN74AUP1G80 as a clock divider and was wondering how to determine the expected output rise/fall times. My CLK input is a 16MHz LVCMOS clock signal operating at either 1.8V or 3.3V. Right now I'm measuring ~10ns rise times on my /Q output (8MHz).
I see that the Switching Characteristics tables specify max frequency (fMAX) and propagation delay (tPD). As the load capacitance increases, fMAX decreases, more so at the lower supply voltages. How is fMAX determined? Are there other devices in this family that may give me a sharper clock edge?
Thanks and regards,