• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 18 subscribers
  • Views 539 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

VME Design and Layout Guidelines to be followed

Madhu Sharma
Expert 2915 points
Other Parts Discussed in Thread: SN74VMEH22501

Hi,


I am using VME buffers with part number SN74VMEH22501 for interfacing VME bus to kintex 7 FPGA. Please let me know if there is any standard desing or layout guidelines to be followed for implementing this.

Regards

Madhu