Issue interfacing SN74AVC2T45 level shifter 125MHz with RGMII signals

Bhavya,

Could you provide a scope shot of the input and output to the TS3DV642 and input and output of the level shifter?

Could you draw where you are putting in the resistor and probing in the system?

Thank you,
Adam

Hi,

We have used the voltage level translator for level shifting 125 MHz clock signal as per shown below:

Si53307------------------------------->33 ohm-----------------> TS3DV642-------------------> 0 OHM---------------->SN74AVC2T245

clock buffer                                                                           analog mux                                                   buffer                       

The input to TS3DV642 (probed at 33 ohm):

 

The output from TS3DV642 (probed at zero ohm):

 

 

Regards,

Bhavya

Bhavya,

Thank you for providing more detail above.  This does not look like normal behavior for the TS3DV642 signal switch.  We would expect the input of the switch to be the same as the output. 

I would like to try and isolate the switch behavior from the system.  What happens if you remove the 0 ohm resistor and disconnect the switch from the level shifter?  Does the input and output behavior remain the same?

Have you tried removing the TS3DV642 from the PCB and blue wire the signal path?  Does this solve the issue?  This will help us isolate if the switch is the root cause. 

Thank you,

Adam

Hi Adam,

I have tried the simulation in Hyperlynx also . It shows the same behaviour. When I remove mux and directly route the signal to level translator the glitch is removed ie the signal has monotonic rise time.

Regards,
Bhavya

Bhavya,

This is unexpected behavior of the device and I'm concerned that you see the same behavior in your simulation. Can you provide your schematic so we can check everything connected to the TS3DV642? All voltages, signal paths, logic, etc.

I will order the TS3DV642 device to our lab so I can double confirm there is no issue with the device. I will use a function generator to create a 125MHz square wave to pass through the TS3DV642 switch. I am 98% confident that my experiment will show no distortion of the 125MHz square wave input to the output of the TS3DV642 but need to eliminate a variable.

There are limited resources around America during this time of year but I will try and make this measurement by next week.

Have you tried using a different TS3DV642 IC on your board?
How many boards have this issue?

Adam

Hi Adam,

There is no distortion when we give the signal only to TS3DV642 , we have checked that. But when we connect TS3DV642 with level translator SN74AVC2T245 , there is distortion in the signal.So the mux performance is good. 

The schematic is as per the block diagram :

We just wanted to know how to solve the issue when  the mux is interfaced with level translator.

Regards,

Bhavya

Bhavya,

That is good news that the TS3DV642 performs as expected.

What happens if you connect the 125MHz clock directly to the level shifter?
Have you tried using a different probe? I had an issue getting a good waveform with a bad probe yesterday.

I will move this post to the level shifter forum for support on the SN74AVC2T245.

Thank you,
Adam

Hi Adam,

We are using differential probe to capture these signals.

Can you please post this query to level shifter forum?

Regards,
Bhavya

Hello Bhavya,

This thread is currently in the level shifter forum. Just to clarify, when you remove the switch and apply the input directly to the voltage translator the distortion is no longer present? So, the issue only occurs when the switch and the translator are interfaced but with each device operating independently there is no distortion?

I will find time in the lab this week to see if I can reproduce the issue.

Hi,

Can you please update me on the progress?

We are nearing the end of design phase.

Regards,

Bhavya

Hello Bhavya,

I noticed that you only have a 0 ohm between the mux and the level translator and no coupling capacitors on your diagram.  In our application and implementation section of the datasheet, we consistently place coupling capacitors on our mainlink and auxiliary channels.  Have you tried populating your circuit with these capacitors?

Hello Bhavya,

We are currently looking into your inquiry and trying to duplicate your results in order to determine how to help you. However, we would like to know why exactly are you using a differential probe for what is typically a single-ended signal?