we are using 1.8 logic level and 3V3 logic level between two system and interface over RGMII interface. And need to support 800Mbps data rate at least.
Question are;
I think we have to use level shift for Tx/Rx Clock and Tx/Rx En but the others are all differential so I don’t think we have to use eight Rx/Tx differential data line. Is it correct?
If we have to use level shifter for eight data transmission line, please let me know why? And what issue happen w/o level shifter.