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SN74AUP1T17: Level translation for 125MHz LVCMOS clock signal

BIPIN BHATT
Intellectual 310 points
Part Number: SN74AUP1T17
Other Parts Discussed in Thread: SN74AXC1T45, SN74AXC8T245

Hi,

We would like to level translate 3.3V 125MHz LVCMOS clock signal to 2.5V level.

I have tried looking into logic device datasheets to identify suitable device to support 125MHz level translation with good signal integrity (i.e. minimal distortion in signal) and remove the jitter.

But unfortunately, the information regarding operating frequency is not available in datasheets. All of the parameters seems provided for low frequencies so am I missing to look any data which gives idea about bandwidth of Logic device.

How can I determine if the SN74AUP1T17 work for 125MHz level translation or not?

This is reference clock for RGMII interface so propogation delay is not important but TpHL and TpLH value should be near so duty cycle remain nearly same as input.

Regards,

Bipin

  • 0
    TI__Guru 56960 points
    Hi Bipin,

    Would you consider using the SN74AXC1T45 which supports up to 200Mhz good enough for the RGMII clock signal.
    Would the other RGMII data signals not require voltage translation? We also have the SN74AXC8T245 supporting the translation 3.3<->2.5V and at 125Mhz.

    Please let me know.
  • 0 in reply to ShreyasRao
    Intellectual 310 points
    Hello Shreyas,

    I have looked into datasheet of SN74AXC1T45. Yes it seems it can support higher datarate up to 500Mbps for 1.8V to 3.3V (up conversion).

    But didn't found bandwidth/datarate specified for 3.3V to 2.5V translation (down conversion).
    I didn't find 200MHz in datasheet, Am I missing anything?

    Is the datarate specification remain same for up and down conversion?

    For the other IO signals, the PHY IC provides seperate power rail which we have connected with 2.5V.

    Best Regards,
    Bipin
  • 0 in reply to BIPIN BHATT
    TI__Guru 56960 points
    Hi Bipin,

    500Mbps is ~250Mhz and for lower voltage of 2.5V, it was safe to say that the device will be able to support a data rate of 125Mhz or 250Mbps suitable for RGMII clock.
    The lower the voltage supply, lower is the data rate supported and higher the supply, the stronger is the drive to support higher datarate.
    Understood on the IO signals doesnt require translation.