SN74LVT125-EP: What is the source or output resistance for this buffer?

Ted,

Your approach to estimate Rout is appropriate.

Have you attempted to simulate with IBIS?  There is not an SN74LVT125 model, but the model for the SN74LVTH125 can be used.   It can be found here: www.ti.com/.../toolssoftware  Possibly try using a series source damping resistor to match with 50ohm impedance without 50ohm end termination.

I am not aware of any of the logic families that can drive into a 50ohm load without significant voltage drop.

Let me get back to you on feasibility of ganging up 2 or more drivers.

Regards,

Wade

Hi Wade,

Thank you very much for the fast response.  I have not simulated with IBIS.  That may be the next thing, presumably the IBIS model will accurately model the buffer output resistance.

I have done some simulations in SPICE to verify the basic theory of either using a 50 ohm end termination or matching the line impedance on the source end by using some combination of buffer output resistance and source series damping resistor.  I guess the 50 ohm end termination is out if there are no logic buffers which can drive it.  Even clock buffers I've looked at seem to have output resistances of 30+ ohms, therefore can't drive 50 ohm end termination.  So sounds like the SN74LVT125-EP with Rseries to match T.L. Zo is my best shot at this point.

Thank you very much for looking into the possibility of ganging multiple drivers.  If possible this would ensure I can really reach a very low output resistance.

Thanks,

Ted

Hi Wade,

Thanks very much for the additional info, the link had some good info I will want to fully digest.

To make sure I understand: When you say my estimated Ron will be pessimistic, your saying it Ron is likely lower than estimated?  For example, I used VOH min = 2V to calculate Ron = 31 ohms.  If VOH is actually 2.3V @ VCC=3V, then Ron = 3V-2.3V/32mA ~22 ohm (assuming the same 32mA drive current)?  Correct?

But one thing I didn't like about the 74LVT125 was the Ron balance isn't very good: For the VOL case I get

Also good news that buffers can be ganged at least in the LVT logic family.

But one thing I didn't like about the 74LVT125 was the Ron balance isn't very good: For the VOL case I estimated Ron = 15.6 ohm using the same method: VOL max/IOL = 0.5V/32mA = 15.6.  Also pessimistic do you think?  

Our application is actually for Space, therefore we are already using both the SN54LVCH244A-SP and SN54AC244-SP Octal Buffers on our board.  Can either of the AC or LVCH logic families be ganged?  Is the LVCH a separate logic family from the LVC, or a subset?

I also stumbled on the SN74LVC2G126-EP Dual Buffer, which I liked due to better Ron balance.  Same question - can LVC buffers be ganged within a single part?

Thanks again for all your help,

Ted

Hi Wade,

Thanks again. I have another question regarding rise time.  What would be the expected output rise/fall time of the 74LVC2G126-EP dual buffer when driving a single, standard CMOS load (high impedance and ~ 5pF capacitance)?  Apparently, this is a number that is normally not specified in the datasheet, probably because it is load dependent?  Does the output rise/fall time depend on the input signal rise/fall time?  In order to simulate this buffer driving my transmission line, I need to assume something for a "nominal" rise/fall output time at the buffer output into the T.L (i.e. ignoring the capacitance associated with multiple loads at various distances down the line since the trace is long enough that it must be treated as a T.L., not as a "lumped element" circuit)

Thanks again, Ted