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Hi,
When power on(VDD exceeds operational voltage, 3V), does Q pin output Low if input pulse is not inputted and RESET pin is High(not reset condition)?
(VDD exceeds oprational voltage, 3V)
My customer seems to be afraid of unstable Q pin output when power on.
Best Regards,
Kuramochi
Hi Kuramochi,
The RESET pin is provided to avoid an unstable Q pin when power is turned on. You need to use the reset pin to avoid unknown condition on the output Q when the device is being powered on.
Thanks!
-Karan