Other Parts Discussed in Thread: SN74LVC1T45-Q1, SN74LVC1G125-Q1
Hello,
Kindly review the attached design using TXS0102QDCURQ1
Thanks,
Melbin
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello,
Kindly review the attached design using TXS0102QDCURQ1
Thanks,
Melbin
Hello,
We are working on a project with TXS0102QDCURQ1 in it.
Kindly review the attached schematics and let me know the review comments.
Hi Melbin,
The TXS0102-Q1 has internal 10-kΩ pull-up resistors on all I/O ports (Ax and Bx), so the external resistors R2 (D), R4, R2630 (D), and R2639 can interfere with the operation of the device. For example, R4 being a 20k pull-down will cause a voltage divider with the 10k internal pull-up resistor and the node will be forced to about 3.3V. I realize that 'D' most likely indicates a non-populated resistor, but I want to mention this to avoid confusion since they may be used later.
It looks like the outputs are remaining active at all times, so the pull-up resistors R2637, R2638, R2640, R2641, and R2642 are not required. The OE pins can be directly connected to VCCA.
Otherwise the schematic looks good. I can't see the load, on either A or B port, so please take note that this device is very sensitive to heavy loads. You should maintain under 70pF at all I/O pins, and avoid long traces. Either of these can result in oscillations.
The TXS has internal pull-up resistors; the pull-down on the MPS signal will not work. I'd suggest the SN74LVC1T45-Q1 for this.
U357 looks OK (if the signals can handle the pull-up resistors), but what is the purpose of U356/U358/U359, where both voltages are the same? Do you want some kind of isolation when one power supply is off? Or might the CAN voltage change later?
For U356/U358/U359 the purpose is to provide isolation between both section.
Here one power may be present when the other is not present, So in order to avoid a leakage path, we implemented this logic.
You do not need level translators to prevent leakage. It is enough to use a plain buffer with overvoltage-tolerant inputs and/or Ioff, e.g., SN74LVC1G125-Q1.
Melbin,
I noticed that you have already posted this. In an effort to consolidate posts on E2E, I have merged the threads.
Best,
Danny