Texas Instruments (TI) Logic support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search logic IC content or ask technical support questions on everything from voltage level translation and transceivers to standard logic gates and specialty logic devices. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions

  • [FAQ] Why does my device not switch at VIH or VIL?

    Other Parts Discussed in Thread: SN74LVC1G08 FAQ: Logic and Voltage Translation > Input Parameters >> Current FAQ What is V IH and V IL ? JEDEC - V IH min is the least positive (most negative) value of high-level input voltage for which operation…

  • [FAQ] How do I size pull-up or pull-down resistors?

    Other Parts Discussed in Thread: SN74AUP1G34 FAQ: Logic and Voltage Translation > Input Parameters >> Current FAQ Pull-up and pull-down resistors are required in many logic systems to provide a valid logic state when a wire connected to a CMOS input…

  • [FAQ] What is the maximum data rate (or operating frequency) for a logic gate or buffer?

    Other Parts Discussed in Thread: SN74LVC1G34 , SN74LVC1G79 FAQ: Logic and Voltage Translation > Timing Parameters >> Current FAQ ** NOTE ** This FAQ is in reference to push-pull output devices. Open-drain outputs will inherently have slower operating…

  • [FAQ] What is the output voltage (VOH or VOL) when the output current is X or the supply voltage is Y?

    FAQ: Logic and Voltage Translation > Output Parameters >> Current FAQ There are circumstances where you might want to know a VOH or VOL Value that is not given. I will describe two cases: If you want VOH for a supply voltage that is not given (for…

  • [FAQ] How do the LSF translators work?

    Other Parts Discussed in Thread: LSF0101 , LSF0002 , LSF0102 , LSF0204 , LSF0204D , LSF0108 , LSF0102-Q1 , LSF0204-Q1 , LSF0108-Q1 FAQ: Logic and Voltage Translation > Voltage Translators >> Current FAQ The LSF family of translators generates more questions…

  • [FAQ] How do I terminate any unused channels of a logic device?

    FAQ: Logic and Voltage Translation > Input Parameters >> Current FAQ CMOS Inputs All CMOS inputs must be terminated at either Vcc or Ground. The inputs of a CMOS device are high-impedance. These terminations can be through a resistor (for example…

  • [FAQ] Are there voltage level translation / level shifter device recommendations for the industry standard interfaces like GPIO, SPI, UART, I2C, MDIO, RGMII, I2S etc?

    FAQ: Logic and Voltage Translation > Voltage Translators >> Current FAQ Here are the voltage level translation device recommendations for various industry standard interfaces: Interface Recommended Device 3.6V Maximum 5.5V Maximum…

  • [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register)

    FAQ: Logic and Voltage Translation > Output Parameters >> Current FAQ Flip-flops, latches, and registers do not have a default state on power up. The output is in an 'unknown' state until data is clocked through. Because of this, SPICE simulation models…

  • [FAQ] How does a slow or floating input affect a CMOS device?

    FAQ: Logic and Voltage Translation > Input Parameters >> Current FAQ There are two primary issues associated with slow and floating inputs. Not sure what a 'floating input' is? Please see our FAQ: What is a floating input or floating node? (1) Shoot…

  • [FAQ] If the OE pin is asserted to maintain Hi-Z at the IO, will it disconnect the internal pull-up resistors in TXS devices?

    FAQ: Logic and Voltage Translation > Voltage Translators >> Current FAQ Yes, the internal pull-up resistors are disconnected once OE is asserted(to enable High impedance on the IO ports) Additionally, if the device supports Vcc isolation feature …

View FAQ threads