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LSF0102: Request characteristics graphic for load capacitance VS maximum speed

Tiger Yeh
Expert 4675 points
Part Number: LSF0102
Other Parts Discussed in Thread: PCA9306,

Hi,

Is there any graphic to show maximum speed V.S. load capacitance for 1.8V to 3.3V level shifter?

Currently, customer is using PCA9306 for 1MHz SMBus application, but it looks PCA9306 could only support up to 400KHz.

LSF0102 is p2p with PCA9306 in DQE package.

However, the maximum load capacitance may be up to more than 400pF, thus they want to check whether it is okay to run 1MHz at this kind of condition?

Please help!

Thanks and Best regards,

Tiger

  • 0
    TI__Mastermind 24805 points

    Tiger,

    I am going to pull in the owner for PCA9306 to comment on this question.

    Best,

    Michael

  • 0
    Guru 269390 points

    The load capacitance must be charged through the pull-up resistor. So the speed is limited by the resulting R-C low-pass filter. The cutoff frequency is 1/(2πRC); digital signals need more analog bandwidth, so you could use 1/(20πRC) as an estimate for the maximum speed.

  • 0 in reply to Clemens Ladisch
    Prodigy 110 points

    Hi Clemens,

    Is there any application document for my reference about that formula?

    here is my understanding.

    R= PU resistance

    C= bus capacitance (include device and trace capacitance)

    so 1/(2πRC) =1/(2*3.14*R*C), right?

    Thanks,

    Yihua

  • 0 in reply to Yihua Lai
    Guru 269390 points

    Yes. (In practice, C is hard to estimate, so you'd just look at the waveform with an oscilloscope and adjust the R.)

  • 0 in reply to Clemens Ladisch
    Prodigy 110 points

    Thank you. Will try to calculate the cut off freq. based on the suggestion.

  • 0 in reply to Clemens Ladisch
    Prodigy 110 points

    Hi,

    Just find two different formulas in the reply.

    one is 1/(2πRC) and the the other one is 1/(20πRC). Which one is the correct one?

    Thanks,

    Yihua

  • 0 in reply to Yihua Lai
    Guru 269390 points

    The first is the −3 dB cutoff for analog signals. The second is an estimate for digital signals.

  • 0 in reply to Clemens Ladisch
    TI__Guru 56370 points

    Just to add an additional comment, the PCA9306 was given the support cap value of 400pF because of the I2C specification for I2C speeds up to 400kHz. At 1MHz the I2C cap limitation moves to 550pF. The device itself can support these cap values but from a system level you would need to calculate the pull up resistor values depending on the bus cap you expect in the system. So the main take away here is higher cap levels are supported from a device perspective but from a system level the I2C spec discourages going past the spec'd limits based on max frequency. Adjusting the pull up resistor values will allow for you to meet I2C rise time requirements but at the cost of higher IoL (resulting in higher VoLs as well).

    Mismatches in cap loading between two sides of the device may also have a parasitic affect where the signal may hang at about Vref1+Vth during fast falling edges. This hang time typically lasts the in low double digit nano seconds and doesn't usually cause any signal integrity issues due to the amount of time is lasts and the I2C deglitching time built into I2C devices.

    -Bobby