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TMS570LC4357: Moving a function to RAM

jimj2713
Expert 2365 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

I am trying to move an ISR, and later more code, to execute out of RAM, but I am getting data-aborts. I see that this has been covered in other E2E conversations,
and I believe I have read them all, but I am still missing something.

I am using HalCogen to generate all of the non-user-code, and the code runs without exceptions in Flash. I made only these changes to place a single ISR in RAM:

In HalCoGen, set the RAM in the MPU as PRIV_RW_USER_RW_EXEC.

In the cmd file, added these lines:
RAMFUNC (RWX): origin=0x08070000 length=0x00010000
.binit align(32) : {} > FLASH0 | FLASH1
.TI.ramfunc align(32) : {} load=FLASH0, run=RAMFUNC, table(BINIT)

Before my ISR, I have:
#pragma CODE_SECTION (func, ".TI.ramfunc")

Note I do not have --ramfuncs=on (as it moves ALL functions to RAM), and I do not have a separate memcopy (to copy the function to RAM), which is not required like the C2000?

I see the RAM-allocation in the map-file, and I can single-step through the ISR (within RAM) using the debugger, but clicking run will cause data-aborts, that seem to occur at different lines of code within the ISR.

Also note the ARM Assembly Language Tools v20.2.0.LTS states there is a Wiki for "Placing functions in RAM", but the URL points back to the general compilers and assembly language tools page, so the pdf essentially points back to itself for help.

Any idea on what I have missed here?

Thanks,

Jim

  • 0
    Guru 92251 points
    jimj2713 said:
    I see the RAM-allocation in the map-file, and I can single-step through the ISR (within RAM) using the debugger, but clicking run will cause data-aborts, that seem to occur at different lines of code within the ISR.

    I had similar issues setting up the TMS570LC4357_sin_cos.zip example in TMS570LC4357: Fastest sin/cos code functions, where that example also copies code into RAM using a ramfunc.

    The following in the main() function in source/HL_sys_main.c contains the fix applied before the program called any functions copied into RAM:

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    /* In _c_int00() _cacheEnable_() is called before __TI_auto_init().
    * I.e. the cache is enabled by the time ramfuncs are copied from FLASH to SRAM, which is effectively self-modifying code.
    * Therefore, need to clean the cache to write-back the ramfuncs into SRAM so that the correct contents is loaded into the
    * instruction cache when the functions are called.
    *
    * Without this cache clean attempting to call the ramfuncs resulted in a pre-fetch abort.
    */
    cache_clean ();
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    And the code for the cache_clean() function is:

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    // Clean the data cache.
    // ARM Architecture Reference Manual
    // B2.2.7 (B2-1286) Performing Cache Maintenance Operations
    // From https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/485953/incorrect-cache-enable-disable-procedure-in-rm57-technical-reference-manual
    asm("CONST_3FF .word 0x3ff");
    asm("CONST_7FFF .word 0x00007fff");
    #define CACHE_CLEAN \
    asm(" MRC p15, #1, r0, c0, c0, #1"); \
    asm(" ANDS R3, R0, #0x07000000"); \
    asm(" MOV R3, R3, LSR #23"); \
    asm(" BEQ Finished"); \
    asm(" MOV R10, #0"); \
    asm("Loop1:"); \
    asm(" ADD R2, R10, R10, LSR #1"); \
    asm(" MOV R1, R0, LSR R2"); \
    asm(" AND R1, R1, #7"); \
    asm(" CMP R1, #2"); \
    asm(" BLT Skip"); \
    asm(" MCR p15, #2, R10, c0, c0, #0"); \
    asm(" ISB"); \
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • +1
    Expert 2365 points

    Wow I would have never found that; I saw your cache_clean, but thought it was related to the speed-test code, and of course I missed your well-written comment; thanks again.

    Jim