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TMS570LC4357: internal pull device vs. external leakage

Matthias Geipel
Prodigy 110 points
Part Number: TMS570LC4357

Hello everyone!

For the internal pullups, the TMS570LC4357 datasheet specifies a current between 5uA and 40uA for VI=VSS. This specification is good to calculate the voltage drop across an external pulldown, pulling the voltage to Low level. Example: For an external 10kOhm pulldown, the voltage drop would be below 0.4V.

The question is now, how to calculate the voltage level, when there is no external pull device, but a CMOS input is connected with a known max. leakage current. In the TMS570LC4357 datasheet, there is no pullup current specification for VI=VIH_min. --> Is the internal 5uA pullup strong enough to pull the line to High level when there is an external leakage current of e.g. 3uA?

In case the internal pullup has to be considered as a constant resistance of 3.3V/5uA=660kOhm max., the resulting voltage level would be 3.3V - 660kOhm*3uA = 1.32V. --> invalid High level

In case the internal pullup can be considered as a constant current source of 5uA up to VI=VIH_min (and maybe as a constant resistance above VI=VIH_min), a leakage current of up to 5uA would generate a valid High level.

Which calculation model has to be applied for the internal pullup?

Is it admissible to apply the datasheet specification of the pullup/down current to VI=VIH_min for pullup and to VI=VIL_max for pulldown?

Best regards,

Matthias  

  • 0
    TI__Guru**** 186286 points

    Hi Matthias,

    Nice questions. I will check the datasheet and come back to you.

  • 0 in reply to QJ Wang
    TI__Guru**** 186286 points

    The internal pulls are primarily provided to hold a unconnected package terminal to a valid logic state. If you add an external pullup or pulldown resistor to a pin, the pull type should be consistent with the internal pull type. Otherwise the logic state is not guaranteed.

  • 0 in reply to QJ Wang
    Prodigy 110 points

    Hi QJ Wang,

    thank you for the answer. Unfortunately, this answer does not really help me. Do you think, that an external pull device has to be added whenever a (low leakage) input is connected to a µC pin? A valid logic state is desired also during reset and SW initialization, before the output buffer is enabled. Usually the internal pull devices should work for this purpose.

  • 0 in reply to Matthias Geipel
    TI__Guru**** 186286 points

    Hi Matthias,

    The internal pulls are weaker by design so that they can be over-driven externally. These internal pulls are sufficient to bias the inputs so that they are not floating. You could add an external pull depending on your requirements of noise immunity or the quality of the input signal. If there is external current leakage, an external pull may be needed.