For the internal pullups, the TMS570LC4357 datasheet specifies a current between 5uA and 40uA for VI=VSS. This specification is good to calculate the voltage drop across an external pulldown, pulling the voltage to Low level. Example: For an external 10kOhm pulldown, the voltage drop would be below 0.4V.
The question is now, how to calculate the voltage level, when there is no external pull device, but a CMOS input is connected with a known max. leakage current. In the TMS570LC4357 datasheet, there is no pullup current specification for VI=VIH_min. --> Is the internal 5uA pullup strong enough to pull the line to High level when there is an external leakage current of e.g. 3uA?
In case the internal pullup has to be considered as a constant resistance of 3.3V/5uA=660kOhm max., the resulting voltage level would be 3.3V - 660kOhm*3uA = 1.32V. --> invalid High level
In case the internal pullup can be considered as a constant current source of 5uA up to VI=VIH_min (and maybe as a constant resistance above VI=VIH_min), a leakage current of up to 5uA would generate a valid High level.
Which calculation model has to be applied for the internal pullup?
Is it admissible to apply the datasheet specification of the pullup/down current to VI=VIH_min for pullup and to VI=VIL_max for pulldown?