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AM2434: AM243x: PRU ICSSG PWM Example?

Johannes von Löwis
Expert 1746 points
Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hello,

is there an example for the TMDS243GPEVM that illustrates how to use the PRU ICSSG PWM module?

From the AM243x TRM I gather that the PWM outputs are affected by compare matches between between IEP_COUNT_REGx and IEP_CMPy_REGz. From section 6.4.10.2 I gather that a CMPx event sets the output x (active state) and a CMP0 event resets the output (initial state). Is that correct? So all ICSSG PWM outputs can enter active state at different times (according to their CMP registers) but enter initial state all at the same time corresponding to CMP0?

Where can I find more information on the PRU ICSSG PWM module? I am having difficulties to understand it based on the information provided in the TRM.

Where do I find the PRU ICSSG PWM outputs in sysconfig?

Can PRU ICSSG PWM generation be used together with industrial internet or EnDat functionality?

Best regards,

Johannes

  • +1
    TI__Mastermind 28788 points

    Hi Johannes,

    Johannes von Löwis said:
    is there an example for the TMDS243GPEVM that illustrates how to use the PRU ICSSG PWM module?

    No, there isn't an example in AM243x MCU+SDK 08.01.00.36.

    Johannes von Löwis said:
    I gather that a CMPx event sets the output x (active state) and a CMP0 event resets the output (initial state). Is that correct?

    Please see the AM64x/AM243x TRM (spruim2c.pdf), Table 6-490. Summary of Entry Events & Table 6-491. State Transition Mapping.

    A CMPx event for any CMP in the PWM Set (PWM signals associated with the PWM module) causes the PWM Set to transition to the Initial to the Active state.

    The PWM Set can be configured to transition from Active to Initial on a CMP0 event, but this is optional. When not configured this way, the PWM Set transitions to the Initial when Trip reset event or hardware reset occurs.

    Johannes von Löwis said:
    So all ICSSG PWM outputs can enter active state at different times (according to their CMP registers) but enter initial state all at the same time corresponding to CMP0?

    Please see the TRM, 6.4.10.2 PRU_ICSSG PWM States Overview:

    "The PWM module has three states (initial, active, and trip),which are shared between PRGn_PWMm_[2:0]_POS
    and PRGn_PWMm_[2:0]_NEG pins (where n = 0 to 2 and m = 0 to 3). The output value for each pin, however, is
    unique and is defined in the ICSSG CFG registers."

    This means the states are associated with all PWMs in a PWM Set, so all PWMs in a Set enter the Active or Initial state at the same time.

    Johannes von Löwis said:
    Where do I find the PRU ICSSG PWM outputs in sysconfig?

    This isn't currently supported in Sysconfig. The ICSSG PWMs need to be manually configured, e.g. using CSL code in <SDK>\source\drivers\hw_include.

    Johannes von Löwis said:
    Can PRU ICSSG PWM generation be used together with industrial internet or EnDat functionality?

    Yes, this should be possible. Industrial Ethernet would be handled on one ICSSG, while Motor Control functionality like EnDat can be handled on another ICSSG. The ICSSG IEP CMPx registers can be directly written from a host like the R5F for controlling the PWM duty cycle.

    Regards,
    Frank

  • 0
    TI__Mastermind 28788 points

    Johannes,

    A typical configuration for the ICSSG PWMs is the following:

    • Write 1/2 PWM period to IEP CMP0
    • Set IEP counter to reset on CMP0 event, provides IEP counter sawtooth
    • Enable IEP CMPx shadow register mode
      • Host core (PRU or R5F) writes to CMPx shadow register
      • CMPx shadow register is copied to CMPx active register on CMP0 event
    • Disable PWM transition to Initial State on IEP CMP0 event, PWMs remain in Active mode on CMP0 event
    • Set ICSSG INTC to generate interrupt to Host core on reaching PWM period. If needed, Host core writes new CMPx to change duty cycle.
    • PWM period is split into “Left” and “Right” half, PWMs are center-aligned

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    Expert 1746 points

    Frank,

    thank you for your explanations. It is still not entirely clear to me but I hope the next version of the TRM will give better explanations. For example, I could not find an explicit definition of the notion of a "PWM Set". How are "PWM Sets" related to the blocks in Figure 6-203? What do the arrows in Figure 6-203 mean?

    Best regards,

    Johannes

  • 0 in reply to Johannes von Löwis
    TI__Mastermind 28788 points

    Hi Johannes,

    Johannes von Löwis said:
    It is still not entirely clear to me but I hope the next version of the TRM will give better explanations.

    Thanks for the feedback. Note there is a "Submit Document Feedback" link on the lower left-hand side on most pages of the TRM.

    Johannes von Löwis said:
    For example, I could not find an explicit definition of the notion of a "PWM Set". How are "PWM Sets" related to the blocks in Figure 6-203?

    Yes, there are 4 Sets of 3 phase motor control outputs, 2 outputs per phase:

    • IEP0: Set 0 & 1 (3*2+3*2 = 12 outputs)
    • IEP1: Set 2 & 3 (3*2+3*2 = 12 outputs)
    Johannes von Löwis said:
    What do the arrows in Figure 6-203 mean?

    I think intent is to show the ICSS-G hardware blocks used to generate the PWM signals, e.g. for Set 0 & 1 this would be IEP0, Slice 0, and the ICSSG CFG hardware blocks.

    Regards,
    Frank