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I need to connect PHY chip (LAN8740A-EN) using MII interface to AM2432 but I am not sure if I am using right balls on AM2432.
I think that I have following two options to connect AM2432 to the PHY chip:
OPTION 1
| BALL | SIGNAL | PHY CHIP PIN |
| Y6 | MIO0_MDC | 16 (MDIO) |
| AA6 | MDIO0_MDIO | 17 (MDC) |
| Y7 | MII0_RXD0 | 11 (RXD0/MODE0) |
| U8 | MII0_RXD1 | 10 (RXD1/MODE1) |
| W8 | MII0_RXD2 | 9 (RXD2/NPME/RMIISEL) |
| V8 | MII0_RXD3 | 8 (RXD3/PHYAD2) |
| Y8 | MII0_RXDV | 26 (RXDV) |
| V13 | MII0_RXER | 13 (RXER/RXD4/PHYAD0) |
| AA7 | MII_MR0_CLK | 7 (RXCLK/PHYAD1) |
| AA8 | MII0_TXD0 | 22 (TXD0) |
| U9 | MII0_TXD1 | 23 (TXD1) |
| W9 | MII0_TXD2 | 24 (TXD2) |
| AA9 | MII0_TXD3 | 25 (TXD3) |
| Y9 | MII0_TXEN | 21 (TXEN) |
| V9 | MII_MT0_CLK | 20 (TXCLK) |
OPTION 2
| BALL | SIGNAL | PHY CHIP PIN |
| Y6 | MIO0_MDC | 16 (MDIO) |
| AA6 | MDIO0_MDIO | 17 (MDC) |
| W11 | MII1_RXD0 | 11 (RXD0/MODE0) |
| V11 | MII1_RXD1 | 10 (RXD1/MODE1) |
| AA12 | MII1_RXD2 | 9 (RXD2/NPME/RMIISEL) |
| Y12 | MII1_RXD3 | 8 (RXD3/PHYAD2) |
| W12 | MII1_RXDV | 26 (RXDV) |
| AA13 | MII1_RXER | 13 (RXER/RXD4/PHYAD0) |
| U11 | MII_MR1_CLK | 7 (RXCLK/PHYAD1) |
| AA10 | MII1_TXD0 | 22 (TXD0) |
| V10 | MII1_TXD1 | 23 (TXD1) |
| U10 | MII1_TXD2 | 24 (TXD2) |
| AA11 | MII1_TXD3 | 25 (TXD3) |
| Y11 | MII1_TXEN | 21 (TXEN) |
| Y10 | MII_MT1_CLK | 20 (TXCLK) |
I need to know if the above selections are correct. In addition I was not able to figure out how to connect the CRS and COL signals. These are pin 14 (CRS) and pin 15 (COL/CRS_DV/MODE2) on the LAN8740A-EN Ethernet PHY chip we intend to use. Can you let me know which balls on AM2432 to use for those two signals.
Hello Igor,
Thank you for your patience.
Have you done any system use case analysis with the SysConfig-PinMux Tool? Link provided below for quick access.
The MII pinmux options you have given are for the PRU_ICSSG1_MII_G_RT and are valid options. There are also valid pinmux options using PRU_ICSSG0_MII_G_RT.
Regardless of which MII interface pinmux option is used, there are assoicated MIIn_CRS and MIIn_COL signals that should be connected to pin 14 (CRS) and pin 15 (COL/CRS_DV/MODE2) on the LAN8740A-EN Ethernet PHY chip respectively. Screenshots from the SysConfig-PinMux Tool implementation of PRU_ICSSG0_MII_G_RT are provided below for reference.
Best Regards,
Zackary Fleenor
