[FAQ] TMS570LC4357: How to use DMA for CAN message transmit and receive?

The CAN module has three message interface registers: IF1, IF2 and IF3.

#1. Using IF3x and DMA to receive message

The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from Message RAM by CPU. The intention of this feature of IF3 is to provide an interface for the DMA to read packets efficiently.

The mailboxes can be enabled for automatic IF3 update. If using message box1 and box2, the bit 0 and bit 1 of DCAN IF3UPD12 should be set.

// Message box 1, 2 configured for auto update
canREG1->IF3UEy[0]= 0x00000003;

The observation flags in the IF3 Observation register should be set:
canREG1->IF3OBS = 0x18;   // Read DATA A & B - 8 bytes 

The source address of DMA packet is: canREG1->IF3DATx[0]

The destination address of DMA packet is: memory locations in SRAM. 

#2. Using IF1x and IF2x and DMA for message transfer

The IF1/IF2 are not suitable for DMA operation. Some clarification is needed in the TRM to list the limitation for using DMA with the DCAN.

If you go to DCAN IF1DATA and IF1DATB registers description, these registers are write-protected meaning that they can only be written in privileged mode. However, the DMA is designed to always operate in user mode. Therefore, the DMA can never write to these DCAN registers. When a write happens from the DMA, the DCAN will simply ignore these writes.

There is no advantage of using DMA to transfer data to the IF1/2 register even if these registers are writeable in the user mode. First, the payload is only 8 bytes. You could have written a store-multiple (STM) instruction to the IF1DATA/IF1DATB register fairly quickly instead of using the DMA where you need to set up the channels and wait for the the DMA to interrupt the CPU when the transfer is complete. Second, the DMA does not know when it is allowed to write to the registers. Before you can write to the IFx registers you will need to poll the busy bit to know whether a transfer between IFx and the message RAM is in progress. The DMA has no such capability. Only CPU does.