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AM2634: Loading the code from Flash to an External SRAM

Wenkai
Prodigy 180 points
Part Number: AM2634

Hello,

We are kind of running out of 2MB RAM space for 4-core application. Does secondary bootloader support loading the code to an external SRAM device? 

Does TI has a plan to use a larger internal RAM for AM2634?

Thanks,

Wenkai

  • 0
    TI__Mastermind 26025 points

    Hi ,

    Are you looking for executing from this external RAM ?

    If this is just for storage then you can consider PSRAM via GPMC interface. You can also use QSPI flash as memory map mode for the same depending on your performance requirements.

    If you are thinking of executing from external RAM then this device might not be a correct solution due to errata -

    Also the XIP is not supported on this device so the flash execution is not possible.

    Please reach out to your TI representative who can suggest devices in alignment to AM263x which will fulfill your application requirements.

    Best Regards,
    Aakash

  • 0 in reply to Aakash Kedia
    Prodigy 180 points

    Hi Aakash,

    Yes, my original question was: if internal SRAM doesn't have enough spaces, can the external SRAM be used for code execution? Sounds like it is not possible for AM2634. 

    And you are not sure about whether or not TI has the plan to use a larger SRAM (>2MB) for AM2634 in the future?

    Thanks,

    Wenkai

  • 0 in reply to Wenkai
    TI__Mastermind 26025 points

    Hi ,

    Wenkai said:
    you are not sure about whether or not TI has the plan to use a larger SRAM (>2MB) for AM2634 in the future?

    TI has plan to support GPMC driver in 9.x for AM263x devices. Although your use case is directed to use the external SRAM for code execution which is not possible due to current errata.

    Let me discuss this internally as well to be 100% sure on this.

    Best Regards,
    Aakash

  • 0 in reply to Aakash Kedia
    Prodigy 180 points

    Hi Aakash,

    By checking the AM263x Errata, I noticed this limitation for QSPI:

    Does it mean even though the flash device has 16MBytes memory space, I only can use up to 8MBytes to store my images? Right now we plan to use up to 15MBytes for the image storage, will it be the issue that the image stored after 8MBytes cannot be loaded to SRAM for running?

    Thanks,

    Wenkai

  • 0 in reply to Wenkai
    TI__Mastermind 26025 points

    Hi ,

    Note this issue is only in memory map mode. So yes, you won't be able to read the data after 8MBytes in this mode. Although in config mode you can still read the data upto 2^32 bytes.

    Best Regards,
    Aakash

  • 0 in reply to Aakash Kedia
    Prodigy 180 points

    Hi Aakash,

    Does TI have any plan to correct this 23 address lines or this will be the situation for a long term?

    I am not very clear what is the difference between mem map mode and config mode. Config mode means indirectly reading through internal registers of the flash chip? Does TI provide the APIs to do this? Is there a TI document describing them?

    Thanks,

    Wenkai

  • 0 in reply to Wenkai
    TI__Mastermind 26025 points

    Hi ,

    Wenkai said:
    Does TI have any plan to correct this 23 address lines or this will be the situation for a long term?

    As I told you, your communication with TI representative (preferably someone from marketing will help you on this). I cannot share more details on future chipset on open forum.

    Wenkai said:
    Config mode means indirectly reading through internal registers of the flash chip?

    Yes that is correct.

    Wenkai said:
    Does TI provide the APIs to do this?

    Currently the APIs are not provided for read although the write APIs are still present and done via Config Reads

    Wenkai said:
    Is there a TI document describing them?

    You can refer to SoC TRM or the SDK documentation for the same.

    Best Regards,
    Aakash