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Original question:

AM2634: Suggestion for SRAM & Flash MPN which is having driver support of AM263x series

AM2634: 256 Mb or larger SRAM & Flash Interfacing with AM2634

Bivin George
Expert 1057 points
Part Number: AM2634
Other Parts Discussed in Thread: SYSCONFIG, , TMDSHSECDOCK-AM263

Tool/software:

Hi

Based on the " TMDSHSECDOCK-AM263", it is shown the compatible flash/SRAM devices include 256 Mb device.

But as per SysConfig tool the address bits available from A0 to A21 (22 bits). To support 256 Mb SRAM, 23 bits are required.

Suggest to which pin of GPMC, the 23th address bit to be connected ?

Can it be connected to CS pin ?

Is AM2634 device drivers available only for SRAM or Flash of size less than 256Mb only ?

Regards

Bivin

  • +1
    TI__Expert 6903 points

    Bivin,

    The memory device included on the TMDSHSECDOCK-AM263 (IS67WVE4M16EBLL-70BLA1) is a 64Mb PSRAM device.

    The 256Mb device, MT28EW256ABA1LPC-0SIT is a NOR Flash device which has slightly different connections than the PSRAM. Refer to Section 2.5.5.3 NOR FLASH of the TMDSHSECDOCK-AM263 User's Guide for details on the hardware connections.

    Right now, the AM2634 device driver for GPMC only supports PSRAM. 

    Regards,

    Brennan

  • 0 in reply to Brennan Hartigan
    Expert 1057 points

    Hi Brennan

    Thanks for the reply.

    I have selected SRAM IC CY62187EV30LL-55BAXI

    As per the response i received in original question, it was confirmed as below.

    https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1381541/am2634-suggestion-for-sram-flash-mpn-which-is-having-driver-support-of-am263x-series

    As per IS67WVE4M16EBLL-70BLA1 IC, this has only one CS pin.

    When i checked SysConfig tool, it shows availability of 4 CS pins for AM2634.

    Will GPMC driver support CY62187EV30LL-55BAXI which is having 2 CS pins ? 

    Please advice.

    Selected IC support read & write in below format also, which is independent on CS pins.

     Will this read & write operation be supported by driver ?

    Regards

    Bivin

  • +1 in reply to Bivin George
    TI__Intellectual 1440 points

    Hi Bivin,


    In case of a 16 bit-non multiplexed memory devices having 'single address cycle', maximum density supported will be 32-Mbit {2M x 16} (on the other side NOR flash MT28EW256ABA1LPC-0SIT has multiple address cycles (more locations can be addressed)and hence GPMC can support more memory density).

    Sorry for the confusion from my previous answer. I noticed the 2 chip selects CY62187EV30LL lately. GPMC can control only one CS at the same time. While checking the timing diagrams shared, I think one workaround idea that can be done in board is to  -

    Method 1: Add a NOT gate prior to CE2 and short it to nCE1. And then control the nCE1 with GPMC_CS0.
    Method 2: From the Logical Block Diagram , since CE2 and nCE1 are connected to an AND Gate , Externally Pulling UP CE2 and nCE1. Connect only nCE1 with GPMC_CS0 will behave as the controllable.

    Please refer to the below interface diagram and Table 13-165. GPMC Pin Multiplexing Options. GPMC0_A1 should be connected to the Least significant Address bit of the 16-bit non-multiplexed device. A1 in the 16-bit non multiplexed memory column refers to the LSB in the memory side (16-bit non multiplexed memory). Some flash vendors use A0 to represent the least significant bit of the memory (as in this case).




    CY7C1071DV33 is a 32 MBit (2M x 16) Static SRAM having only one chip select (CEn).Please check if this part can be used for your application.



    Best Regards,
    Rijohn