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Hello TI team,
What is the difference between SW warm reset and SW POR reset on AM2432?
If we choose to use SW warm reset in watchdog's NMI ISR, is there any corner case that SW warm reset would not be able to reset the MCU to recover from failure state?
Thanks,
Hong
Hey Hong,
Apologies for not responding to this thread earlier. We discussed these details during our weekly sync meeting. To recap:
1) SW PORz Reset (SW_MCU_RESETz) (Equivalent to MCU_RESETz pin): This reset isn't supported in your use case since the MCU domain is not in an isolated state. Since there is only a single combined MAIN domain here, the MCU_PORz pin should be used to reset the entire device.
SW Warm Reset (SW_MAIN_WARMRESET) (Equivalent to MAIN_RESETz_REQ pin):
MCU Domain Action | MAIN Domain Action |
All modules in MCU are reset except for modules and MMR bits which are reset only on PORz. IOs are not affected. M4FSS core is reset. Upon reset deassertion, MCU domain must be reconfigured by R5 cores (Boot Processor) in MAIN domain. |
All modules in MAIN are reset except for modules and MMR bits which are reset only on PORz. IOs are not affected. All processor cores are reset (A53SS, DMSC, and R5FSS). Upon reset deassertion, device goes through full boot. Reason for this reset is captured in Reset status register. During device boot-up, secondary boot loader will read the Reset Status register and MCU ACTIVE MAGIC WORD to decide whether to reconfigure M4FSS accordingly. |
2) The SW reset is triggerable from any ISR, we are not currently aware of any corner case where a reset would fail to propagate.
Best Regards,
Zackary Fleenor
Hello Zackary,
Thanks for the explanation.
We updated SW main warm reset to SW MCU warm reset in our project based on TI's suggestion, and have not observed any issues so far.
Thanks again,
Hong