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AM2634-Q1: Autosar : ADC ISR not triggered on period match event of PWM

Ashish Sebastian
Prodigy 225 points
Part Number: AM2634-Q1

Platform :

MCAL : MCAL_AM263x_08.06.02

Configurations :

XBAR Configured :
MCU Config : XBAR0_OUT0 -> EPWM0_INT
MCU Config : XBAR0_OUT1 -> ADC0_INT1

INT Enabled :
Os_Hal_INTC_EnableSource(146)
Os_Hal_INTC_EnableSource(147)

Notifications Enabled :
ADC and PWM channel notification

Configured PWM : Period Match Interrupt (CDD based - Not Autosar Based)
Compare SS : CMPA and CMPC registers configured
Trigger SS : Configured to trigger EPWM0.SOCA

Configured ADC : to be triggered by EPWM0
Trigger Source EPWM0
Interrupt based result collection

Configured OS ISR:
Cat0 ISR for PWM0
Cat1 ISR for ADC0

Observations :

PWM0.ETFLG shows SOCA was generated
ADCSOCFLG.SOC0 updated
ADCRESULT0 seems to be updated.

Miss-match in expectation :
ADC INT not triggered
ADC notification not triggered; as ADC INT not triggered

Additional tries:

Configured ADC as ISR CAT2; still the same behavior.

I have query related to the MCU generation; as well.

A quick help here would be much appreciated please. Please do also let me know if a call is possible to address the topic.

  • 0
    Prodigy 225 points

    MoM : 22/06/2023:

    • Adc_EnableHardwareTrigger will start configuring the registers from SOC15 Sub-modules onwards
      • It will configure the SOC sub-modules based on the configured group priority.
        • Ex: If Grp0 -> lower prio and Grp1 -> higher prio; then Grp0 SOC updated in SOC15 register  then Grp1 SOC updated in SOC14 register
    • Adc_EnableHardwareTrigger for One-Shot conversion; would need to be called cyclically as the current MCAL implementation would clear the SOC configuration info from ISR. This behaviour would need to be re-looked by TI internally.
    • Adc_EnableHardwareTrigger for Continuous conversion is not supported due to Autosar limitation in he MCAL.
    • Mcu generation for the XBAR interrupt mapping for ADC channels seems to be incorrect; which would need to be fixed.

    Further action points: 

    • Check the VIM status dump for interrupts mapped out of OS context.
      • If its generating the interrupts correctly; then Vector needs to be contacted for further debugging.
    • Need to know why HW trigger details are not getting captured in the corresponding SOC14 and SOC13 registers; for the other ADC channels; even though they are configured.
  • 0 in reply to Ashish Sebastian
    TI__Genius 12080 points

    Hi Ashish,

    Please find the details below shared by our ADC expert.

    The Interrupt Flag to be verified in ADC module, to confirm whether interrupt occurred or not:

    The below provided package has details of the MCAL ADC module working for Cross bar OUT 2 (Interrupt source 148).

    /cfs-file/__key/communityserver-discussions-components-files/908/MCAL_5F00_AM263x_5F00_08.06.02.zip

     

    Application provided here is on top of the MCAL Release package 8.6.2. Changes we did are:

    HW UNIT 0 used here (Similar to your use case application) and

    XBAR OUT 2 (148)  is mapped to HW UNIT 0 , INT 0 (as shown below)

     

    Please validate package has the same behavior at your end and confirm it.

    Thanks And Regards,

    Sunil Kumar M S 

  • 0 in reply to Sunil Kumar M S
    Prodigy 225 points

    Adc_PBcfg.c
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    /*
    *
    * Copyright (c) 2023 Texas Instruments Incorporated
    *
    * All rights reserved not granted herein.
    *
    * Limited License.
    *
    * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
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    * The patent license shall not apply to any combinations which include this software,
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    * No hardware patent is licensed hereunder.
    *
    * Redistributions must preserve existing copyright notices and reproduce this license
    * (including the above copyright notice and the disclaimer and (if applicable) source
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    AdcApp.c
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    /* ======================================================================
    * Copyright (C) 2022-2023 Texas Instruments Incorporated
    *
    * All rights reserved. Property of Texas Instruments Incorporated.
    * Restricted rights to use, duplicate or disclose this code are
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    /**
    * \file AdcApp.c
    *
    * \brief This file contains the Adc test example
    *
    */
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    I have set up 2 more HW triggers by updating  Adc_PBCfg.c manually in the shared files for covering the below scenarios : 

    • Adc Grp3 -> Triggered based on PWM0_SOCB -> Triggering XBAR 149 -> Triggering ISR Adc_ADCINT2_IrqUnit0
    • Adc Grp4 -> Triggered based on PWM1_SOCA -> Triggering XBAR 150 -> Triggering ISR Adc_ADCINT3_IrqUnit0

    In both these cases I have kept the break points at new ISRs; but the control does not reach the ISRs.

  • 0 in reply to Ashish Sebastian
    TI__Genius 12080 points

    Hi Ashish,

    Please find the patch attached modified according to your testcase and verified.

    /cfs-file/__key/communityserver-discussions-components-files/908/Adc_5F00_Testing.zip

    Thanks And Regards,

    Sunil Kumar M S

  • 0 in reply to Sunil Kumar M S
    Prodigy 225 points

    Just an update wrt the HW/SW triggered ADC EoC handing of the SoC Subsystem of the ADC module as I understood from TI. Thanks for Clarifying the concept Pratik.

    It would be helpful to capture it in release notes or delivery notes of the ADC delivery; so that it would be easier to understand the MCAL design decisions; that could be helpful during debugging.

  • 0 in reply to Ashish Sebastian
    Prodigy 225 points

    ADC Cat2 interrupts are getting triggered with the MCAL package 8.6.2.1, based on the above concept. Closing the ticket.