• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 30 subscribers
  • Views 404 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2634-Q1: Autosar : PWM Channel does not trigger 2 events simultaneously

Ashish Sebastian
Prodigy 225 points
Part Number: AM2634-Q1

Hi Team,

We are trying to make the Event trigger sub-system of the PWM channel to trigger 2 events on counter compare match :

  • PWM interrupt AND
  • ADC SoC

We have configured the ETSEL as below, to trigger the events, when the CMPA reg matches CNT reg; using the EPWM_Enable() API as in the Adc_app example app.

Expected behavior :

  • Both the events should get triggered
  • ADC conversion data should be parallelly available in the ADC_RESULTS register; when processing the PWM as high prio interrupt.

Observed behavior :

  • PWM Cat0 and CAT2 ISR is working correctly when TBCNT counter reaches 0; and the ISRs are getting triggered. But this is happening independently; based on PWM_Init config.
  • On configuring PWM module for multiple trigger using EPWM_Enable(); the PWM Cat0/CAT2 ISR does not operate at all.
  • 0
    TI__Genius 15435 points

    Hi,

    I have heard back from the expert, here's their response.

    For more then one event trigger, we need to set the interrupts as below:

     EPWM_setInterruptSource(CONFIG_EPWM0_BASE_ADDR, EPWM_INT_TBCTR_ETINTMIX, mixedSource);

    EPWM_INT_TBCTR_ETINTMIX ==> Indicates the mixed interrupts

    mixedSource ==> Indicates the setting of below register "ETINTMIXEN". The value shall be as shown below:

    To enable the events at CMPA and CMPC while incrementing, the values should be 0b 0000 0000 0010 0100  è 0x23

    mixedSource è value should be 0x23.

    Similarly of  “EPWM_setADCTriggerSource” can used for multiple triggers with SOCA:

    EPWM_setADCTriggerSource(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A, EPWM_SOC_TBCTR_MIXED_EVENT, mixedSource);

    EPWM_SOC_TBCTR_MIXED_EVENT ==> Indicates the mixed interrupts

    mixedSource ==> Indicates the setting of below register " ETSOCAMIXEN". The value shall be as shown below:

    Similarly of  “EPWM_setADCTriggerSource” can used for multiple triggers with SOCB:

    EPWM_setADCTriggerSource(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A, EPWM_SOC_TBCTR_MIXED_EVENT, mixedSource);

    EPWM_SOC_TBCTR_MIXED_EVENT ==> Indicates the mixed interrupts

    mixedSource ==> Indicates the setting of below register " ETSOCBMIXEN". The value shall be as shown below:

  • 0 in reply to Kowshik Gudimetla
    Prodigy 225 points

    Hello ,

    I am a bit confused about the example :

    To enable the events at CMPA and CMPC while incrementing, the values should be 0b 0000 0000 0010 0100  è 0x23

    mixedSource è value should be 0x23.

    Are you intending to set the regs CAU and CCU in "ETINTMIXEN"? If so; my understanding is that you should set the mixedsource to 0x44 based on the bit positions. Is my understanding incorrect?

    Now based on my understanding I have made the changes as you have suggested. But still notice only ADC ISRs getting triggered. 

    OS config : 

    PWM ISR : Cat2, Prio 0 (Not triggered)

    ADC ISRs : Cat2, Prio 1 (All of them are triggered)

    Please do let me know if my understanding is incorrect. If not, I would request you to please arrange for a debug call as this is very critical for a demo to the customer in the upcoming week; please.

  • 0 in reply to Ashish Sebastian
    TI__Genius 15435 points

    Hi Ashish,

    Is this resolved from Pratik over the call? Do you have the summary/notes you would like to share here so I can share to the respective owner and get their feedback?

    Thanks

  • +1 in reply to Kowshik Gudimetla
    Prodigy 225 points

    Hi Kowshik,

    Thanks very much for the quick and timely support that I received from Pratik. 

    The main reason that caused PWM interrupt not to trigger was the over-writing of the registers associated with PWM channel; through the API Epwm_Enable(). (Not sure if this is a known behavior of PWM registers). However, this API would still need to be called for updating the triggering of the ADC SoC.

    We observed that the PWM MCAL implementation design decisions were not known until the meeting with Pratik. Capturing them based on the understanding so far, so it could be helpful for anyone else as well:

    PWM_Init :

    * Initializes CMPA and CMPB registers based on period and duty cycle config

    * Implies TBCTR = TBPRD and TBCTR = 0 is not possible with MCAL

     

    PWM_EnableNotification :

    * Enable pwm interrupt (based on rising or falling edge on both edges) - this means that we would not need to enable PWM INT with Epwm_Enable AND

    * Enables Interrupt notification

     

    Epwm_Enable :

    * Is used to configure the PWM Event Trigger Sub-Module registers (for Adc_SoC settings); as ASR MCAL configurations have limitations for this setting

    * EPWM_setADCTriggerSource () has to be called according to Output Channel selection:

        * If Output ch == BothA and B then ADC_TrigSrc API should be called with EPWM_SOC_TBCTR_MIXED_EVENT else PWM ISR/ADC ISR would not get triggered

        * If Output ch == A OR B then ADC_TrigSrc API should be called with EPWM_SOC_TBCTR_U_CMPA/EPWM_SOC_TBCTR_U_CMPB