Had to select unknown part number because it wasn't in the drop down list... TMS470PLF111.
Looking for any technical manuals for GIO, CLass 2, watch dog, FMPKEY, flash wrapper, and watch dog, J-tag
Also looking for .cnf file for HAL Code Gen
Thanks,
Jamie
Please read the below register memory map again. PortA (or Port0) starts at 0x34, PortB (or Port1) starts at 0x54 and PortC (or Port2) starts at 0x74. If you want to set PortC then it starts at 0x74 for GIODIRC, not 0x54. 0x54 is for GIODIRB. In another word, you are playing with PortB rather than PortC. This is why you don't see any pins toggled for PortC.
This is your GIO dump aligned to 32-bit word.
but do you have a MibSPI manual for the closest chip that I have?
I thought I gave you the below TRM in my last reply. This TRM is for TMS470PVF24xB device which shares the same architecture as your device. The MibSPI chapter should be the same between the two devices.
MIB offset plus 0x3C is being written to toggle pins in my code, but in the manual I have it says that is reserved?
Which document are you referring to?
In the TRM I attached, MibSPI + 0x3C is the SPIDAT1 register. First, this is not reserved. Second, this is the data register for SPI functional mode. This register is not used for GIO.
In order to use MibSPI pins for GIO, you need to configure registers SPIPC0, SPIPC1, SPIPC2, SPIPC3, SPIPC4 and SPIPC5 registers.
1. Program SPIPC0 to use MibSPI pins for GIO pins. By default after reset, it is already in GIO mode.
2. Program SPIPC1 to use MibSPI pins as either input or output pins. If you want to use MibSPI pins for GIO output pins, you need to write 1 to the corresponding pins.
3. Program either SPIPC3 (DOUT), SPIPC4 (SET) and SPIPC5 (CLR) to set or clear the pins like the way you did for GIO module.
4. Read SPIPC2 (DIN) register for the state of the pins.
Please go through the TRM for details.
They issue is it’s never written to the Dout, the existing codes only writing to Ox3C after init. And the isn’t much documentation for that offset bits 16-23 CNSR no idea what they do
CSNR field is described in TRM. However, I have no way to know what the prior author of your code was intending to do with writing to 0x3C after init. If you want to use MibSPI pins for GPIO, you will need to follow the instructions I provided in my last reply. All I can say is that the SPIDAT1 register at 0x3C is intended for MibSPI functional operation. You write to the TXDATA[15:0] to cause the data to shift out of the MOSI pin. CSNR field is to specify which chip select is active for the transfer.
Ok yes but chip select of what exactly?
This is a MibSPI device with the capability to connect to multiple slave devices. Each slave device will be selected by an individual CS signal. You write to CSNR field to specify which slave device you want to transmit the data to. The CSNR field and as matter of fact the entire SPIDAT1 register has nothing to do with GIO operation. You will need to consult with the prior author on what slave device is intended for communication. BTW, how do you know the code is only writing to CSNR field, and not the entire register?
Could the 0x3C be some sort of testing procedure for certain pins? This function is called using a tester to momentarily turn on the pins. And I traced one of the pins back to a GIO pin as well.
Again, that is your application. I wouldn't know. Perhaps, after init, your application was trying to send some test data or real data to slave to establish a communication. I have seen many applications that will send data to other devices via CAN, SPI, UART etc.
Can you use mibspi to test pins other modules like GIO internally? Or maybe the pins on the board are tied to two pins gio, and mibspi?
You need to check if the code was doing some type of loopback selftest. Check your code if it is reading data from SPIBUF at 0x40. If you see this, you may be in some loopback mode. Read the below section if your code is doing test mode.
