Part Number: TMS570LS1224
Other Parts Discussed in Thread: TMS320F28035, HALCOGEN,
Hello, I've been using PWM for driving BLDC motor for quiet some time and during testing I've noticed some strange behavior.
I have detected where is the casue, I would like to know why its happening.
(note: pwm_u is EPwm4Regs, pwm_v is EPwm7Regs and pwm_w is EPwm5Regs
PWM is set at 20kHz freqency using Up-down mode, so far all changes in PWM periphery had same results)
/* Basic PWM periphery settings */
pwm_u->TBPRD = 2000; // Period = 4001 TBCLK counts (20 kHz)
pwm_u->TBPHS.half.TBPHS = 0; // Set Phase register to zero
pwm_u->TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
pwm_u->TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
pwm_u->TBCTL.bit.PRDLD = TB_SHADOW;
pwm_u->TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
pwm_u->CMPCTL.bit.SHDWAMODE = CC_SHADOW;
pwm_u->CMPCTL.bit.SHDWBMODE = CC_SHADOW;
pwm_u->CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
pwm_u->CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
pwm_u->AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM4A
pwm_u->AQCTLA.bit.CAD = AQ_CLEAR;
This is called inside interrupt to change which of PWM outputs should modulate :
/* To prevent unintentional transistor short-circuit during force event */
pwm_u->DBCTL.bit.OUT_MODE = OUT_DISABLED; // 0 - Disable Dead Band for output A
pwm_v->DBCTL.bit.OUT_MODE = OUT_DISABLED; // 0 - Disable Dead Band for output A
pwm_w->DBCTL.bit.OUT_MODE = OUT_DISABLED; // 0 - Disable Dead Band for output A
/* Main part */
pwm_u->aqcsfrc.reg_value.csfa = PWM_AQ_SWF_NONE; // enable PWM on A output
pwm_u->aqcsfrc.reg_value.csfb = PWM_AQ_SWF_LO;
pwm_v->aqcsfrc.reg_value.csfa = PWM_AQ_SWF_LO;
pwm_v->aqcsfrc.reg_value.csfb = PWM_AQ_SWF_HI;
pwm_w->aqcsfrc.reg_value.csfa = PWM_AQ_SWF_LO;
pwm_w->aqcsfrc.reg_value.csfb = PWM_AQ_SWF_LO;
pwm_u->DBCTL.bit.HALFCYCLE = ENABLED; // 1
pwm_u->DBCTL.bit.IN_MODE = IN_MODE_RA_FA; // 0 - source for both falling-edge and rising-edge
pwm_u->DBCTL.bit.POLSEL = ACTIVE_HI_COMP; // 2 - Active High Complementary (B is inverted)
pwm_u->DBCTL.bit.OUT_MODE = PWM_DB_OUT_FULL_ENABLE; // 3 - Enable Dead Band for both outputs
pwm_v->DBCTL.bit.HALFCYCLE = DISABLED; // 0
pwm_v->DBCTL.bit.IN_MODE = IN_MODE_RA_FA; // 0 - source for both falling-edge and rising-edge
pwm_v->DBCTL.bit.POLSEL = ACTIVE_HI; // 0 - Active High (neither A nor B is inverted)
pwm_v->DBCTL.bit.OUT_MODE = PWM_DB_OUT_A_ENABLE; // 2 - Enable Dead Band for output A
pwm_w->DBCTL.bit.HALFCYCLE = DISABLED; // 0
pwm_w->DBCTL.bit.IN_MODE = IN_MODE_RA_FA; // 0 - source for both falling-edge and rising-edge
pwm_w->DBCTL.bit.POLSEL = ACTIVE_HI; // 0 - Active High (neither A nor B is inverted)
pwm_w->DBCTL.bit.OUT_MODE = PWM_DB_OUT_A_ENABLE; // 2 - Enable Dead Band for output A
And this is result:
The main problem causing glitch is ironically in part, which is suppose to prevent this kind of things (from my point of view) and that is disabling dead band before forcing Action-Qualifier.
Now another strange thing is that when I am increasing duty cycle ( above 35 % ) the pulse on channel B is long (they are overlaping).
Over 50% duty the complementary pulse is working and behave as it should which is weird :
So now to my question. When I remove line which is disabling DBCTL on phase U (ePWM4A) then complementary channel B starts working properly in every duty (not only above 50%).
Can someone explain to me why is this happening? Why cannot I safely first disable dead band and couple of instructions later turn it on without getting weird glitch?
Also I have been using TMS320F28035 with same settings of PWM and same code(with of course some minor changes due to the fact its different processor) and that thing didnt occur there.
