MSPM0G1107: SPI CS pin control issue

Nian Yang

Prodigy 50 points

Part Number: MSPM0G1107

Hi TI experts,

I want to control my peripheral device by SPI.

However, the CS pin has a high-low action every byte.

It causes the peripheral device not to perform correctly.

If CS pin keep low level, it can perform correctly.

How could I fix it issue?

Thanks for your time and reply.

BR,

Nian

over 2 years ago

0 Keith Barkley over 2 years ago

Guru 42205 points

Are you using 4 wire or 3 wire SPI? If 4 wire, you might need to switch to 3 and program the CS on your own.

+1 Jace H over 2 years ago in reply to Keith Barkley

TI__Guru 56685 points

Hello Nian,

Double check which SPI mode you have setup the SPI module to be in. If it's in the TI mode, CS will go high on the last SPI CLK of any given transfer. If you are in Motorola Format, CS pin will go high between transfers depending on the specific SPO and SPH settings. If SPH = 1, then the CS line should be held low throughout a continuous transfer. In other cases, it will raise high in between transfer to allow for peripheral write.

See section 17.2.3.1 in the TRM for details.

0 Nian Yang over 2 years ago in reply to Keith Barkley

Prodigy 50 points

Hi Keith,

I using 4 wire. I know the method that switch to 3 and program the CS on my own, but I thought SPI could handle this CS low.

0 Nian Yang over 2 years ago in reply to Jace H

Prodigy 50 points

Hi Jace,

Thanks for your remind, I thought it was just controlling the SCK edge and ignoring the CS control.

0 Nian Yang over 2 years ago in reply to Jace H

Prodigy 50 points

Hi Jace,

I modified SPH = 1 and CS pin was held low through transfer.

The waveform as below.

But there is a problem about SCLK signal is continued.

My peripheral device requires a interval between byte to byte, such as my second image of above post.

Could the MSPG01107 SPI implement it?

BR,
Nian

0 Jace H over 2 years ago in reply to Nian Yang

TI__Guru 56685 points

Nian,

If you need the pause, then you would need to setup with just a FIFO of 1 and fill between transfers I think. There is no setting within the peripheral to do such a pause. I'm not sure how the CS pin logic will hold for that use case. You may have to manually control it as well if going this route.

0 Nian Yang over 2 years ago in reply to Jace H

Prodigy 50 points

Hi Jace,

I have set TX FIFO to a FIFO of 1 in the above waveform.

That's fine. I control CS pin manually and it is work.

Thanks.

BR,
Nian

Arm-based microcontrollers

Arm-based microcontrollers forum

MSPM0G1107: SPI CS pin control issue