TM4C1294NCPDT: TM4C1294XL EVK

//*****************************************************************************
//
// bl_config.h - The configurable parameters of the boot loader.
//
// Copyright (c) 2013-2016 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// 
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 2.1.3.156 of the DK-TM4C129X Firmware Package.
//
//*****************************************************************************

#ifndef __BL_CONFIG_H__
#define __BL_CONFIG_H__

//*****************************************************************************
//
// The following defines are used to configure the operation of the boot
// loader.  For each define, its interactions with other defines are described.
// First is the dependencies (in other words, the defines that must also be
// defined if it is defined), next are the exclusives (in other words, the
// defines that can not be defined if it is defined), and finally are the
// requirements (in other words, the defines that must be defined if it is
// defined).
//
// The following defines must be defined in order for the boot loader to
// operate:
//
//     One of CAN_ENABLE_UPDATE, ENET_ENABLE_UPDATE, I2C_ENABLE_UPDATE,
//            SSI_ENABLE_UPDATE, UART_ENABLE_UPDATE, or USB_ENABLE_UPDATE
//     APP_START_ADDRESS
//     VTABLE_START_ADDRESS
//     FLASH_PAGE_SIZE
//     STACK_SIZE
//
//*****************************************************************************

//*****************************************************************************
//
// The frequency of the crystal used to clock the microcontroller.
//
// This defines the crystal frequency used by the microcontroller running the
// boot loader.  If this is unknown at the time of production, then use the
// UART_AUTOBAUD feature to properly configure the UART.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define CRYSTAL_FREQ            25000000

//*****************************************************************************
//
// The starting address of the application.  This must be a multiple of 1024
// bytes (making it aligned to a page boundary).  A vector table is expected at
// this location, and the perceived validity of the vector table (stack located
// in SRAM, reset vector located in flash) is used as an indication of the
// validity of the application image.
//
// The flash image of the boot loader must not be larger than this value.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define APP_START_ADDRESS       0x00004000

//*****************************************************************************
//
// The address at which the application locates its exception vector table.
// This must be a multiple of 1024 bytes (making it aligned to a page
// boundary).  Typically, an application will start with its vector table and
// this value should be set to APP_START_ADDRESS.  This option is provided to
// cater for applications which run from external memory which may not be
// accessible by the NVIC (the vector table offset register is only 30 bits
// long).
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define VTABLE_START_ADDRESS    0x00004000

//*****************************************************************************
//
// The size of a single, erasable page in the flash.  This must be a power
// of 2.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define FLASH_PAGE_SIZE         0x4000

//*****************************************************************************
//
// The amount of space at the end of flash to reserved.  This must be a
// multiple of 1024 bytes (making it aligned to a page boundary).  This
// reserved space is not erased when the application is updated, providing
// non-volatile storage that can be used for parameters.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define FLASH_RSVD_SPACE        0x00000800

//*****************************************************************************
//
// The number of words of stack space to reserve for the boot loader.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define STACK_SIZE              256

//*****************************************************************************
//
// The number of words in the data buffer used for receiving packets.  This
// value must be at least 3.  If using auto-baud on the UART, this must be at
// least 20.  The maximum usable value is 65 (larger values will result in
// unused space in the buffer).
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define BUFFER_SIZE             20

//*****************************************************************************
//
// Enables updates to the boot loader.  Updating the boot loader is an unsafe
// operation since it is not fully fault tolerant (losing power to the device
// part way though could result in the boot loader no longer being present in
// flash).
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define ENABLE_BL_UPDATE

//*****************************************************************************
//
// Enables runtime and download CRC32 checking of the main firmware image.
// If this is defined, the boot loader will scan the main firmware image for
// an image information header (stored immediately above the vector table and
// marked by the words 0xFF01FF02 and 0xFF03FF04).  If the header is found and
// the CRC32 value it contains matches that calculated for the image, the
// firmware is run.  If the CRC32 does not match or the image information
// is not found, the boot loader retains control and waits for a new download.
// To aid debugging, if this option is used without ENFORCE_CRC being set, the
// image will also be booted if the header is present but the length field is
// set to 0xFFFFFFFF, typically indicating that the firmware file has not been
// run through the post-processing tool which inserts the length and CRC values.
//
// Note that firmware images intended for use with CRC checking must have been
// built with an 8 word image header appended to the top of the vector table
// and the binary must have been processed by a tool such as tools/binpack.exe
// to ensure that the required length (3rd word) and CRC32 (4th word) fields
// are populated in the header.
//
// Depends on: ENFORCE_CRC
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CHECK_CRC

//*****************************************************************************
//
// This definition may be used alongside CHECK_CRC to remove the debug behavior
// which will allow an image with an uninitialized header to be run.  With
// ENFORCE_CRC defined firmware images will only be booted if they contain a
// valid image information header and if the embedded CRC32 in that header
// matches the calculated value.
//
// Depends on: None
// Exclusive of: None
// Requires: CHECK_CRC
//
//*****************************************************************************
//#define ENFORCE_CRC

//*****************************************************************************
//
// This definition will cause the the boot loader to erase the entire flash on
// updates to the boot loader or to erase the entire application area when the
// application is updated.  This erases any unused sections in the flash before
// the firmware is updated.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define FLASH_CODE_PROTECTION

//*****************************************************************************
//
// Enables the call to decrypt the downloaded data before writing it into
// flash.  The decryption routine is empty in the reference boot loader source,
// which simply provides a placeholder for adding an actual decryption
// algorithm.  Although this option is retained for backwards compatibility, it
// is recommended that a decryption function be specified using the newer hook
// function mechanism and BL_DECRYPT_FN_HOOK instead.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define ENABLE_DECRYPTION

//*****************************************************************************
//
// Enables support for the MOSCFAIL handler in the NMI interrupt.
//
// Depends on: None
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define ENABLE_MOSCFAIL_HANDLER

//*****************************************************************************
//
// Enables the pin-based forced update check.  When enabled, the boot loader
// will go into update mode instead of calling the application if a pin is read
// at a particular polarity, forcing an update operation.  In either case, the
// application is still able to return control to the boot loader in order to
// start an update.  For applications which need to perform more complex
// checking than is possible using a single GPIO, a hook function may be
// provided using BL_CHECK_UPDATE_FN_HOOK instead.
//
// Depends on: None
// Exclusive of: None
// Requires: FORCED_UPDATE_PERIPH, FORCED_UPDATE_PORT, FORCED_UPDATE_PIN,
//           FORCED_UPDATE_POLARITY
//
//*****************************************************************************
//#define ENABLE_UPDATE_CHECK

//*****************************************************************************
//
// The GPIO module to enable in order to check for a forced update.  This will
// be one of the SYSCTL_RCGC2_GPIOx values, where "x" is replaced with the port
// name (such as B).  The value of "x" should match the value of "x" for
// FORCED_UPDATE_PORT.
//
// Depends on: ENABLE_UPDATE_CHECK
// Exclusive of: None
// Requries: None
//
//*****************************************************************************
//#define FORCED_UPDATE_PERIPH    SYSCTL_RCGC2_GPIOB

//*****************************************************************************
//
// The GPIO port to check for a forced update.  This will be one of the
// GPIO_PORTx_BASE values, where "x" is replaced with the port name (such as
// B).  The value of "x" should match the value of "x" for
// FORCED_UPDATE_PERIPH.
//
// Depends on: ENABLE_UPDATE_CHECK
// Exclusive of: None
// Requries: None
//
//*****************************************************************************
//#define FORCED_UPDATE_PORT      GPIO_PORTB_BASE

//*****************************************************************************
//
// The pin to check for a forced update.  This is a value between 0 and 7.
//
// Depends on: ENABLE_UPDATE_CHECK
// Exclusive of: None
// Requries: None
//
//*****************************************************************************
//#define FORCED_UPDATE_PIN       4

//*****************************************************************************
//
// The polarity of the GPIO pin that results in a forced update.  This value
// should be 0 if the pin should be low and 1 if the pin should be high.
//
// Depends on: ENABLE_UPDATE_CHECK
// Exclusive of: None
// Requries: None
//
//*****************************************************************************
//#define FORCED_UPDATE_POLARITY  0

//*****************************************************************************
//
// This enables a weak pull-up or pull-down for the GPIO pin used in a forced
// update.  Only one of FORCED_UPDATE_WPU or FORCED_UPDATE_WPD should be
// defined, or neither if a weak pull-up or pull-down is not required.
//
// Depends on: ENABLE_UPDATE_CHECK
// Exclusive of: None
// Requries: None
//
//*****************************************************************************
//#define FORCED_UPDATE_WPU
//#define FORCED_UPDATE_WPD

//*****************************************************************************
//
// This enables the use of the GPIO_LOCK mechanism for configuration of
// protected GPIO pins (for example JTAG pins).  If this value is not defined,
// the locking mechanism will not be used.  The only legal values for this
// feature are GPIO_LOCK_KEY for Fury devices and GPIO_LOCK_KEY_DD for all
// other devices except Sandstorm devices, which do not support this feature.
//
// Depends on: ENABLE_UPDATE_CHECK
// Exclusive of: None
// Requries: None
//
//*****************************************************************************
//#define FORCED_UPDATE_KEY       GPIO_LOCK_KEY
//#define FORCED_UPDATE_KEY       GPIO_LOCK_KEY_DD

//*****************************************************************************
//
// Selects the UART as the port for communicating with the boot loader.
//
// Depends on: None
// Exclusive of: CAN_ENABLE_UPDATE, ENET_ENABLE_UPDATE, I2C_ENABLE_UPDATE,
//               SSI_ENABLE_UPDATE, USB_ENABLE_UPDATE
// Requires: UART_AUTOBAUD or UART_FIXED_BAUDRATE, UART_CLOCK_ENABLE, 
//           UARTx_BASE, UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_BASE, 
//           UART_RXPIN_PCTL, UART_RXPIN_POS, UART_TXPIN_CLOCK_ENABLE,
//           UART_TXPIN_BASE, UART_TXPIN_PCTL and UART_TXPIN_POS
//
//*****************************************************************************
//#define UART_ENABLE_UPDATE

//*****************************************************************************
//
// Enables automatic baud rate detection.  This can be used if the crystal
// frequency is unknown, or if operation at different baud rates is desired.
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: UART_FIXED_BAUDRATE
// Requires: None
//
//*****************************************************************************
//#define UART_AUTOBAUD

//*****************************************************************************
//
// Selects the baud rate to be used for the UART.
//
// Depends on: UART_ENABLE_UPDATE, CRYSTAL_FREQ
// Exclusive of: UART_AUTOBAUD
// Requires: None
//
//*****************************************************************************
//#define UART_FIXED_BAUDRATE     115200

//*****************************************************************************
//
// Selects the clock enable for the UART peripheral module
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UARTx_BASE
//
//*****************************************************************************
//#define UART_CLOCK_ENABLE     SYSCTL_RCGCUART_R0

//*****************************************************************************
//
// Selects the base address of the UART peripheral module
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_CLOCK_ENABLE
//
//*****************************************************************************
//#define UARTx_BASE     UART0_BASE

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to UART RX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_RXPIN_BASE, UART_RXPIN_PCTL and UART_RXPIN_POS
//
//*****************************************************************************
//#define UART_RXPIN_CLOCK_ENABLE     SYSCTL_RCGCGPIO_R0

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to UART RX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_PCTL and UART_RXPIN_POS
//
//*****************************************************************************
//#define UART_RXPIN_BASE     GPIO_PORTA_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to UART RX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_BASE and UART_RXPIN_POS
//
//*****************************************************************************
//#define UART_RXPIN_PCTL     0x1

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to UART RX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_BASE and UART_RXPIN_PCTL
//
//*****************************************************************************
//#define UART_RXPIN_POS     0

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to UART TX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_TXPIN_BASE, UART_TXPIN_PCTL and UART_TXPIN_POS
//
//*****************************************************************************
//#define UART_TXPIN_CLOCK_ENABLE     SYSCTL_RCGCGPIO_R0

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to UART TX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_PCTL and UART_TXPIN_POS
//
//*****************************************************************************
//#define UART_TXPIN_BASE     GPIO_PORTA_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to UART TX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_BASE and UART_TXPIN_POS
//
//*****************************************************************************
//#define UART_TXPIN_PCTL     0x1

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to UART TX pin
//
// Depends on: UART_ENABLE_UPDATE
// Exclusive of: None
// Requires: UART_TXPIN_CLOCK_ENABLE, UART_TXPIN_BASE and UART_TXPIN_PCTL
//
//*****************************************************************************
//#define UART_TXPIN_POS     1

//*****************************************************************************
//
// Selects the SSI port as the port for communicating with the boot loader.
//
// Depends on: None
// Exclusive of: CAN_ENABLE_UPDATE, ENET_ENABLE_UPDATE, I2C_ENABLE_UPDATE,
//               UART_ENABLE_UPDATE, USB_ENABLE_UPDATE
// Requires: SSI_CLOCK_ENABLE, SSIx_BASE, SSI_CLKPIN_CLOCK_ENABLE, 
//           SSI_CLKPIN_BASE, SSI_CLKPIN_PCTL, SSI_CLKPIN_POS, 
//           SSI_FSSPIN_CLOCK_ENABLE, SSI_FSSPIN_BASE, SSI_FSSPIN_PCTL,
//           SSI_FSSPIN_POS, SSI_MISOPIN_CLOCK_ENABLE, SSI_MISOPIN_BASE,
//           SSI_MISOPIN_PCTL, SSI_MISOPIN_POS, SSI_MOSIPIN_CLOCK_ENABLE,
//           SSI_MOSIPIN_BASE, SSI_MOSIPIN_PCTL and SSI_MOSIPIN_POS
//
//*****************************************************************************
//#define SSI_ENABLE_UPDATE

//*****************************************************************************
//
// Selects the clock enable for the SSI peripheral module
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSIx_BASE
//
//*****************************************************************************
//#define SSI_CLOCK_ENABLE          SYSCTL_RCGCSSI_R0

//*****************************************************************************
//
// Selects the base address of the SSI peripheral module
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_CLOCK_ENABLE
//
//*****************************************************************************
//#define SSIx_BASE          SSI0_BASE

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to SSI CLK pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_CLKPIN_BASE, SSI_CLKPIN_PCTL and SSI_CLKPIN_POS
//
//*****************************************************************************
//#define SSI_CLKPIN_CLOCK_ENABLE          SYSCTL_RCGCGPIO_R0

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to SSI CLK pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_CLKPIN_CLOCK_ENABLE, SSI_CLKPIN_PCTL and SSI_CLKPIN_POS
//
//*****************************************************************************
//#define SSI_CLKPIN_BASE          GPIO_PORTA_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to SSI CLK pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_CLKPIN_CLOCK_ENABLE, SSI_CLKPIN_BASE and SSI_CLKPIN_POS
//
//*****************************************************************************
//#define SSI_CLKPIN_PCTL          0x2

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to SSI CLK pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_CLKPIN_CLOCK_ENABLE, SSI_CLKPIN_BASE and SSI_CLKPIN_PCTL
//
//*****************************************************************************
//#define SSI_CLKPIN_POS          2

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to SSI FSS pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_FSSPIN_BASE, SSI_FSSPIN_PCTL and SSI_FSSPIN_POS
//
//*****************************************************************************
//#define SSI_FSSPIN_CLOCK_ENABLE          SYSCTL_RCGCGPIO_R0

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to SSI FSS pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_FSSPIN_CLOCK_ENABLE, SSI_FSSPIN_PCTL and SSI_FSSPIN_POS
//
//*****************************************************************************
//#define SSI_FSSPIN_BASE          GPIO_PORTA_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to SSI FSS pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_FSSPIN_CLOCK_ENABLE, SSI_FSSPIN_BASE and SSI_FSSPIN_POS
//
//*****************************************************************************
//#define SSI_FSSPIN_PCTL          0x2

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to SSI FSS pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_FSSPIN_CLOCK_ENABLE, SSI_FSSPIN_BASE and SSI_FSSPIN_PCTL
//
//*****************************************************************************
//#define SSI_FSSPIN_POS          3

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to SSI MISO pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_MISOPIN_BASE, SSI_MISOPIN_PCTL and SSI_MISOPIN_POS
//
//*****************************************************************************
//#define SSI_MISOPIN_CLOCK_ENABLE          SYSCTL_RCGCGPIO_R0

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to SSI MISO pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_MISOPIN_CLOCK_ENABLE, SSI_MISOPIN_PCTL and SSI_MISOPIN_POS
//
//*****************************************************************************
//#define SSI_MISOPIN_BASE          GPIO_PORTA_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to SSI MISO pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_MISOPIN_CLOCK_ENABLE, SSI_MISOPIN_BASE and SSI_MISOPIN_POS
//
//*****************************************************************************
//#define SSI_MISOPIN_PCTL          0x2

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to SSI MISO pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_MISOPIN_CLOCK_ENABLE, SSI_MISOPIN_BASE and SSI_MISOPIN_PCTL
//
//*****************************************************************************
//#define SSI_MISOPIN_POS          5

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to SSI MOSI pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_MOSIPIN_BASE, SSI_MOSIPIN_PCTL and SSI_MOSIPIN_POS
//
//*****************************************************************************
//#define SSI_MOSIPIN_CLOCK_ENABLE          SYSCTL_RCGCGPIO_R0

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to SSI MOSI pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_MOSIPIN_CLOCK_ENABLE, SSI_MOSIPIN_PCTL and SSI_MOSIPIN_POS
//
//*****************************************************************************
//#define SSI_MOSIPIN_BASE          GPIO_PORTA_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to SSI MOSI pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_MOSIPIN_CLOCK_ENABLE, SSI_MOSIPIN_BASE and SSI_MOSIPIN_POS
//
//*****************************************************************************
//#define SSI_MOSIPIN_PCTL          0x2

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to SSI MOSI pin
//
// Depends on: SSI_ENABLE_UPDATE
// Exclusive of: None
// Requires: SSI_MOSIPIN_CLOCK_ENABLE, SSI_MOSIPIN_BASE and SSI_MOSIPIN_PCTL
//
//*****************************************************************************
//#define SSI_MOSIPIN_POS          4

//*****************************************************************************
//
// Selects the I2C port as the port for communicating with the boot loader.
//
// Depends on: None
// Exclusive of: CAN_ENABLE_UPDATE, ENET_ENABLE_UPDATE, SSI_ENABLE_UPDATE,
//               UART_ENABLE_UPDATE, USB_ENABLE_UPDATE
// Requires: I2C_SLAVE_ADDR, I2C_CLOCK_ENABLE, I2Cx_BASE, 
//           I2C_SCLPIN_CLOCK_ENABLE, I2C_SCLPIN_BASE, I2C_SCLPIN_PCTL,
//           I2C_SCLPIN_POS, I2C_SDAPIN_CLOCK_ENABLE, I2C_SDAPIN_BASE,
//           I2C_SDAPIN_PCTL and I2C_SDAPIN_POS
//
//*****************************************************************************
//#define I2C_ENABLE_UPDATE

//*****************************************************************************
//
// Specifies the I2C address of the boot loader.
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define I2C_SLAVE_ADDR          0x42

//*****************************************************************************
//
// Selects the clock enable for the I2C peripheral module
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2Cx_BASE
//
//*****************************************************************************
//#define I2C_CLOCK_ENABLE          SYSCTL_RCGCI2C_R0

//*****************************************************************************
//
// Selects the base address of the I2C peripheral module
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_CLOCK_ENABLE
//
//*****************************************************************************
//#define I2Cx_BASE          I2C0_BASE
//#define I2Cx_BASE			      I2C0_BASE

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to I2C SCL pin
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_SCLPIN_BASE, I2C_SCLPIN_PCTL and I2C_SCLPIN_POS
//
//*****************************************************************************
//#define I2C_SCLPIN_CLOCK_ENABLE          SYSCTL_RCGCGPIO_R1

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to I2C SCL pin
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_SCLPIN_CLOCK_ENABLE, I2C_SCLPIN_PCTL and I2C_SCLPIN_POS
//
//*****************************************************************************
//#define I2C_SCLPIN_BASE          GPIO_PORTB_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to I2C SCL pin
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_SCLPIN_CLOCK_ENABLE, I2C_SCLPIN_BASE and I2C_SCLPIN_POS
//
//*****************************************************************************
//#define I2C_SCLPIN_PCTL          0x3

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to I2C SCL pin
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_SCLPIN_CLOCK_ENABLE, I2C_SCLPIN_BASE and I2C_SCLPIN_PCTL
//
//*****************************************************************************
//#define I2C_SCLPIN_POS          2

//*****************************************************************************
//
// Selects the clock enable for the GPIO corresponding to I2C SDA pin
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_SDAPIN_BASE, I2C_SDAPIN_PCTL and I2C_SDAPIN_POS
//
//*****************************************************************************
//#define I2C_SDAPIN_CLOCK_ENABLE          SYSCTL_RCGCGPIO_R1

//*****************************************************************************
//
// Selects the base address for the GPIO corresponding to I2C SDA pin
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_SDAPIN_CLOCK_ENABLE, I2C_SDAPIN_PCTL and I2C_SDAPIN_POS
//
//*****************************************************************************
//#define I2C_SDAPIN_BASE          GPIO_PORTB_BASE

//*****************************************************************************
//
// Selects the port control value for the GPIO corresponding to I2C SDA pin
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_SDAPIN_CLOCK_ENABLE, I2C_SDAPIN_BASE and I2C_SDAPIN_POS
//
//*****************************************************************************
//#define I2C_SDAPIN_PCTL          0x3

//*****************************************************************************
//
// Selects the pin number for the GPIO corresponding to I2C SDA pin
//
// Depends on: I2C_ENABLE_UPDATE
// Exclusive of: None
// Requires: I2C_SDAPIN_CLOCK_ENABLE, I2C_SDAPIN_BASE and I2C_SDAPIN_PCTL
//
//*****************************************************************************
//#define I2C_SDAPIN_POS          3

//*****************************************************************************
//
// Selects Ethernet update via the BOOTP/TFTP protocol.
//
// Depends on: None
// Exclusive of: CAN_ENABLE_UPDATE, I2C_ENABLE_UPDATE, SSI_ENABLE_UPDATE,
//               UART_ENABLE_UPDATE, USB_ENABLE_UPDATE
// Requires: CRYSTAL_FREQ
//
//*****************************************************************************
#define ENET_ENABLE_UPDATE

//*****************************************************************************
//
// Enables the use of the Ethernet status LED outputs to indicate traffic and
// connection status.
//
// Depends on: ENET_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define ENET_ENABLE_LEDS

//*****************************************************************************
//
// Specifies the hard coded MAC address for the Ethernet interface.  There are
// six individual values (ENET_MAC_ADDR0 through ENET_MAC_ADDR5) that provide
// the six bytes of the MAC address, where ENET_MAC_ADDR0 though ENET_MAC_ADDR2
// provide the organizationally unique identifier (OUI) and ENET_MAC_ADDR3
// through ENET_MAC_ADDR5 provide the extension identifier.  If these values
// are not provided, the MAC address will be extracted from the user registers.
//
// Depends on: ENET_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define ENET_MAC_ADDR0          0x70
#define ENET_MAC_ADDR1          0xFF
#define ENET_MAC_ADDR2          0x76
#define ENET_MAC_ADDR3          0x1F
#define ENET_MAC_ADDR4          0x13
#define ENET_MAC_ADDR5          0x0D

//*****************************************************************************
//
// Specifies the name of the BOOTP server from which to request information.
// The use of this specifier allows a board-specific BOOTP server to co-exist
// on a network with the DHCP server that may be part of the network
// infrastructure.  The BOOTP server provided by Texas Instruments requires
// that this be set to "stellaris".
//
// Depends on: ENET_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
#define ENET_BOOTP_SERVER       "tiva"

//*****************************************************************************
//
// Selects USB update via Device Firmware Update class.
//
// Depends on: None
// Exclusive of: CAN_ENABLE_UPDATE, ENET_ENABLE_UPDATE, I2C_ENABLE_UPDATE,
//               SSI_ENABLE_UPDATE, UART_ENABLE_UPDATE,
// Requires: CRYSTAL_FREQ, USB_VENDOR_ID, USB_PRODUCT_ID, USB_DEVICE_ID,
//           USB_MAX_POWER
//
//*****************************************************************************
//#define USB_ENABLE_UPDATE

//*****************************************************************************
//
// The USB vendor ID published by the DFU device.  This value is the TI
// Tiva vendor ID.  Change this to the vendor ID you have been assigned by the
// USB-IF.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_VENDOR_ID           0x1cbe

//*****************************************************************************
//
// The USB device ID published by the DFU device.  If you are using your own
// vendor ID, chose a device ID that is different from the ID you use in
// non-update operation.  If you have sublicensed TI's vendor ID, you must
// use an assigned product ID here.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_PRODUCT_ID          0x00ff

//*****************************************************************************
//
// Selects the BCD USB device release number published in the device
// descriptor.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_DEVICE_ID           0x0001

//*****************************************************************************
//
// Sets the maximum power consumption that the DFU device will report to the
// USB host in the configuration descriptor.  Units are milliamps.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_MAX_POWER           150

//*****************************************************************************
//
// Specifies whether the DFU device reports to the host that it is self-powered
// (defined as 0) or bus-powered (defined as 1).
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_BUS_POWERED         1

//*****************************************************************************
//
// Specifies whether the target board uses a multiplexer to select between USB
// host and device modes.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: USB_MUX_PERIPH, USB_MUX_PORT, USB_MUX_PIN, USB_MUX_DEVICE
//
//*****************************************************************************
//#define USB_HAS_MUX

//*****************************************************************************
//
// Specifies the GPIO peripheral containing the pin which is used to select
// between USB host and device modes.  The value is of the form
// SYSCTL_RCGC2_GPIOx, where GPIOx represents the required GPIO port.
//
// Depends on: USB_ENABLE_UPDATE, USB_HAS_MUX
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_MUX_PERIPH          SYSCTL_RCGC2_GPIOH

//*****************************************************************************
//
// Specifies the GPIO port containing the pin which is used to select between
// USB host and device modes.  The value is of the form GPIO_PORTx_BASE, where
// PORTx represents the required GPIO port.
//
// Depends on: USB_ENABLE_UPDATE, USB_HAS_MUX
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_MUX_PORT            GPIO_PORTH_BASE

//*****************************************************************************
//
// Specifies the GPIO pin number used to select between USB host and device
// modes.  Valid values are 0 through 7.
//
// Depends on: USB_ENABLE_UPDATE, USB_HAS_MUX
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_MUX_PIN             2

//*****************************************************************************
//
// Specifies the state of the GPIO pin required to select USB device-mode
// operation.  Valid values are 0 (low) or 1 (high).
//
// Depends on: USB_ENABLE_UPDATE, USB_HAS_MUX
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_MUX_DEVICE          1

//*****************************************************************************
//
// Specifies whether the target board requires configuration of the pin used
// for VBUS.  This applies to Blizzard class and later devices.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: USB_VBUS_PERIPH, USB_VBUS_PORT, USB_VBUS_PIN
//
//*****************************************************************************
//#define USB_VBUS_CONFIG

//*****************************************************************************
//
// Specifies the GPIO peripheral containing the pin which is used for VBUS.
// The value is of the form SYSCTL_RCGCGPIO_Rx, where the Rx represents
// the required GPIO port.  This applies to Blizzard class and later 
// devices.
//
// Depends on: USB_ENABLE_UPDATE, USB_VBUS_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_VBUS_PERIPH          SYSCTL_RCGCGPIO_R1

//*****************************************************************************
//
// Specifies the GPIO port containing the pin which is used for VBUS.  The value
// is of the form GPIO_PORTx_BASE, where PORTx represents the required GPIO
// port.
//
// Depends on: USB_ENABLE_UPDATE, USB_VBUS_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_VBUS_PORT            GPIO_PORTB_BASE

//*****************************************************************************
//
// Specifies the GPIO pin number used for VBUS.  Valid values are 0 through 7.
//
// Depends on: USB_ENABLE_UPDATE, USB_VBUS_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_VBUS_PIN             1

//*****************************************************************************
//
// Specifies whether the target board requires configuration of the pin used
// for ID.  This applies to Blizzard class and later devices.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: USB_ID_PERIPH, USB_ID_PORT, USB_ID_PIN
//
//*****************************************************************************
//#define USB_ID_CONFIG

//*****************************************************************************
//
// Specifies the GPIO peripheral containing the pin which is used for ID.
// The value is of the form SYSCTL_RCGCGPIO_Rx, where the Rx represents
// the required GPIO port.  This applies to Blizzard class and later 
// devices.
//
// Depends on: USB_ENABLE_UPDATE, USB_ID_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_ID_PERIPH          SYSCTL_RCGCGPIO_R1

//*****************************************************************************
//
// Specifies the GPIO port containing the pin which is used for ID.  The value
// is of the form GPIO_PORTx_BASE, where PORTx represents the required GPIO
// port.
//
// Depends on: USB_ENABLE_UPDATE, USB_ID_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_ID_PORT            GPIO_PORTB_BASE

//*****************************************************************************
//
// Specifies the GPIO pin number used for ID.  Valid values are 0 through 7.
//
// Depends on: USB_ENABLE_UPDATE, USB_ID_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_ID_PIN             0

//*****************************************************************************
//
// Specifies whether the target board requires configuration of the pin used
// for DP.  This applies to Blizzard class and later devices.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: USB_DP_PERIPH, USB_DP_PORT, USB_DP_PIN
//
//*****************************************************************************
//#define USB_DP_CONFIG

//*****************************************************************************
//
// Specifies the GPIO peripheral containing the pin which is used for DP.
// The value is of the form SYSCTL_RCGCGPIO_Rx, where the Rx represents
// the required GPIO port.  This applies to Blizzard class and later 
// devices.
//
// Depends on: USB_ENABLE_UPDATE, USB_DP_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_DP_PERIPH          SYSCTL_RCGCGPIO_R10

//*****************************************************************************
//
// Specifies the GPIO port containing the pin which is used for DP.  The value
// is of the form GPIO_PORTx_BASE, where PORTx represents the required GPIO
// port.
//
// Depends on: USB_ENABLE_UPDATE, USB_DP_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_DP_PORT            GPIO_PORTL_BASE

//*****************************************************************************
//
// Specifies the GPIO pin number used for DP.  Valid values are 0 through 7.
//
// Depends on: USB_ENABLE_UPDATE, USB_DP_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_DP_PIN             6

//*****************************************************************************
//
// Specifies whether the target board requires configuration of the pin used
// for DM.  This applies to Blizzard class and later devices.
//
// Depends on: USB_ENABLE_UPDATE
// Exclusive of: None
// Requires: USB_DM_PERIPH, USB_DM_PORT, USB_DM_PIN
//
//*****************************************************************************
//#define USB_DM_CONFIG

//*****************************************************************************
//
// Specifies the GPIO peripheral containing the pin which is used for DM.
// The value is of the form SYSCTL_RCGCGPIO_Rx, where the Rx represents
// the required GPIO port.  This applies to Blizzard class and later 
// devices.
//
// Depends on: USB_ENABLE_UPDATE, USB_DM_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_DM_PERIPH          SYSCTL_RCGCGPIO_R10

//*****************************************************************************
//
// Specifies the GPIO port containing the pin which is used for DM.  The value
// is of the form GPIO_PORTx_BASE, where PORTx represents the required GPIO
// port.
//
// Depends on: USB_ENABLE_UPDATE, USB_DM_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_DM_PORT            GPIO_PORTL_BASE

//*****************************************************************************
//
// Specifies the GPIO pin number used for DM.  Valid values are 0 through 7.
//
// Depends on: USB_ENABLE_UPDATE, USB_DM_CONFIG
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define USB_DM_PIN             7

//*****************************************************************************
//
// Selects an update via the CAN port.
//
// Depends on: None
// Exclusive of: ENET_ENABLE_UPDATE, I2C_ENABLE_UPDATE, SSI_ENABLE_UPDATE,
//               UART_ENABLE_UPDATE, USB_ENABLE_UPDATE
// Requires: CAN_RX_PERIPH, CAN_RX_PORT, CAN_RX_PIN, CAN_TX_PERIPH,
//           CAN_TX_PORT, CAN_TX_PIN, CAN_BIT_RATE, CRYSTAL_FREQ.
//
//*****************************************************************************
//#define CAN_ENABLE_UPDATE

//*****************************************************************************
//
// Enables the UART to CAN bridging for use when the CAN port is selected for
// communicating with the boot loader.
//
// Depends on: CAN_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CAN_UART_BRIDGE

//*****************************************************************************
//
// The GPIO module to enable in order to configure the CAN0 Rx pin.  This will
// be one of the SYSCTL_RCGC2_GPIOx values, where "x" is replaced with the port
// name (such as B).  The value of "x" should match the value of "x" for
// CAN_RX_PORT.
//
// Depends on: CAN_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CAN_RX_PERIPH           SYSCTL_RCGC2_GPIOA

//*****************************************************************************
//
// The GPIO port used to configure the CAN0 Rx pin.  This will be one of the
// GPIO_PORTx_BASE values, where "x" is replaced with the port name (such as
// B).  The value of "x" should match the value of "x" for CAN_RX_PERIPH.
//
// Depends on: CAN_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CAN_RX_PORT             GPIO_PORTA_BASE

//*****************************************************************************
//
// The GPIO pin that is shared with the CAN0 Rx pin.  This is a value between 0
// and 7.
//
// Depends on: CAN_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CAN_RX_PIN              4

//*****************************************************************************
//
// The GPIO module to enable in order to configure the CAN0 Tx pin.  This will
// be one of the SYSCTL_RCGC2_GPIOx values, where "x" is replaced with the port
// name (such as B).  The value of "x" should match the value of "x" for
// CAN_TX_PORT.
//
// Depends on: CAN_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CAN_TX_PERIPH           SYSCTL_RCGC2_GPIOA

//*****************************************************************************
//
// The GPIO port used to configure the CAN0 Tx pin.  This will be one of the
// GPIO_PORTx_BASE values, where "x" is replaced with the port name (such as
// B).  The value of "x" should match the value of "x" for CAN_TX_PERIPH.
//
// Depends on: CAN_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CAN_TX_PORT             GPIO_PORTA_BASE

//*****************************************************************************
//
// The GPIO pin that is shared with the CAN0 Tx pin.  This is a value between 0
// and 7.
//
// Depends on: CAN_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CAN_TX_PIN              5

//*****************************************************************************
//
// The bit rate used on the CAN bus.  This must be one of 20000, 50000, 125000,
// 250000, 500000, or 1000000.  The CAN bit rate must be less than or equal to
// the crystal frequency divided by 8 (CRYSTAL_FREQ / 8).
//
// Depends on: CAN_ENABLE_UPDATE
// Exclusive of: None
// Requires: None
//
//*****************************************************************************
//#define CAN_BIT_RATE            1000000

//*****************************************************************************
//
// Performs application-specific low level hardware initialization on system
// reset.  If hooked, this function will be called immediately after the boot
// loader code relocation completes.  An application may perform any required
// low-level hardware initialization during this function.  Note that the
// system clock has not been set when this function is called.  Initialization
// that assumes the system clock is set may be performed in the BL_INIT_FN_HOOK
// function instead.
//
// void MyHwInitFunc(void);
//
//*****************************************************************************
//#define BL_HW_INIT_FN_HOOK      MyHwInitFunc

//*****************************************************************************
//
// Performs application-specific initialization on system reset.  If hooked,
// this function will be called during boot loader initialization to perform
// any board- or application-specific initialization which is required.  The
// function is called following a reset immediately after the selected boot
// loader peripheral has been configured and the system clock has been set.
//
// void MyInitFunc(void);
//
//*****************************************************************************
//#define BL_INIT_FN_HOOK         MyInitFunc

//*****************************************************************************
//
// Performs application-specific reinitialization on boot loader entry via SVC.
// If hooked, this function will be called during boot loader reinitialization
// to perform any board- or application-specific initialization which is
// required.  The function is called following boot loader entry from an
// application, after any system clock rate adjustments have been made.
//
// void MyReinitFunc(void);
//
//*****************************************************************************
//#define BL_REINIT_FN_HOOK       MyReinitFunc

//*****************************************************************************
//
// Informs an application that a download is starting.  If hooked, this
// function will be called when a firmware download is about to begin.  The
// function is called after the first data packet of the download is received
// but before it has been written to flash.
//
// void MyStartFunc(void);
//
//*****************************************************************************
//#define BL_START_FN_HOOK        MyStartFunc

//*****************************************************************************
//
// Informs an application of download progress.  If hooked, this function will
// be called periodically during a firmware download to provide progress
// information.  The function is called after each data packet is received from
// the host.  Parameters provide the number of bytes of data received and, in
// cases other than Ethernet update, the expected total number of bytes in the
// download (the TFTP protocol used by the Ethernet boot loader does not send
// the final image size before the download starts so in this case the ulTotal
// parameter is set to 0 to indicate that the size is unknown).
//
// void MyProgressFunc(unsigned long ulCompleted, unsigned long ulTotal);
//
//*****************************************************************************
//#define BL_PROGRESS_FN_HOOK     MyProgressFunc

//*****************************************************************************
//
// Informs an application that a download has completed.  If hooked, this
// function will be called when a firmware download has just completed.  The
// function is called after the final data packet of the download has been
// written to flash.
//
// void MyEndFunc(void);
//
//*****************************************************************************
//#define BL_END_FN_HOOK          MyEndFunc

//*****************************************************************************
//
// Allows an application to perform in-place data decryption during download.
// If hooked, this function will be called to perform in-place decryption of
// each data packet received during a firmware download.
//
// void MyDecryptionFunc(unsigned char *pucBuffer, unsigned long ulSize);
//
// This value takes precedence over ENABLE_DECRYPTION.  If both are defined,
// the hook function defined using BL_DECRYPT_FN_HOOK is called rather than the
// previously-defined DecryptData() stub function.
//
//*****************************************************************************
//#define BL_DECRYPT_FN_HOOK      MyDecryptionFunc

//*****************************************************************************
//
// Allows an application to force a new firmware download.  If hooked, this
// function will be called during boot loader initialization to determine
// whether a firmware update should be performed regardless of whether a valid
// main code image is already present.  If the function returns 0, the existing
// main code image is booted (if present), otherwise the boot loader will wait
// for a new firmware image to be downloaded.
//
// unsigned long MyCheckUpdateFunc(void);
//
// This value takes precedence over ENABLE_UPDATE_CHECK} if both are defined.
// If you wish to perform a GPIO check in addition to any other update check
// processing required, the GPIO code must be included within the hook function
// itself.
//
//*****************************************************************************
//#define BL_CHECK_UPDATE_FN_HOOK MyCheckUpdateFunc

//*****************************************************************************
//
// Allows an application to replace the flash block erase function.  If hooked,
// this function will be called whenever a block of flash is to be erased.  The
// function must erase the block and wait until the operation has completed.
// The size of the block which will be erased is defined by FLASH_BLOCK_SIZE.
//
// void MyFlashEraseFunc(unsigned long ulBlockAddr);
//
//*****************************************************************************
//#define BL_FLASH_ERASE_FN_HOOK  MyFlashEraseFunc

//*****************************************************************************
//
// Allows an application to replace the flash programming function.  If hooked,
// this function will be called to program the flash with firmware image data
// received during download operations.  The function must program the supplied
// data and wait until the operation has completed.
//
// void MyFlashProgramFunc(unsigned long ulDstAddr,
//                         unsigned char *pucSrcData,
//                         unsigned long ulLength);
//
//*****************************************************************************
//#define BL_FLASH_PROGRAM_FN_HOOK MyFlashProgramFunc

//*****************************************************************************
//
// Allows an application to replace the flash error clear function.  If hooked,
// this function must clear any flash error indicators and prepare to detect
// access violations that may occur in a future erase or program operations.
//
// void MyFlashClearErrorFunc(void);
//
//*****************************************************************************
//#define BL_FLASH_CL_ERR_FN_HOOK MyFlashClearErrorFunc

//*****************************************************************************
//
// Reports whether or not a flash access violation error has occurred.  If
// hooked, this function will be called after flash erase or program
// operations.  The return code indicates whether or not an access violation
// error occurred since the last call to the function defined by
// BL_FLASH_CL_ERR_FN_HOOK, with 0 indicating no errors and non-zero indicating
// an error.
//
// unsigned long MyFlashErrorFunc(void);
//
//*****************************************************************************
//#define BL_FLASH_ERROR_FN_HOOK  MyFlashErrorFunc

//*****************************************************************************
//
// Reports the total size of the device flash.  If hooked, this function will
// be called to determine the size of the supported flash device.  The return
// code is the number of bytes of flash in the device.  Note that this does not
// take into account any reserved space defined via the FLASH_RSVD_SPACE value.
//
// unsigned long MyFlashSizeFunc(void);
//
//*****************************************************************************
//#define BL_FLASH_SIZE_FN_HOOK   MyFlashSizeFunc

//*****************************************************************************
//
// Reports the address of the first byte after the end of the device flash.  If
// hooked, this function will be called to determine the address of the end of
// valid flash.  Note that this does not take into account any reserved space
// defined via the FLASH_RSVD_SPACE value.
//
// unsigned long MyFlashEndFunc(void);
//
//*****************************************************************************
//#define BL_FLASH_END_FN_HOOK    MyFlashEndFunc

//*****************************************************************************
//
// Checks whether the start address and size of an image are valid.  If hooked,
// this function will be called when a new firmware download is about to start.
// Parameters provided are the requested start address for the new download
// and, when using protocols which transmit the image length in advance, the
// size of the image that is to be downloaded.  The return code will be
// non-zero to indicate that the start address is valid and the image will fit
// in the available space, or 0 if either the address is invalid or the image
// is too large for the device.
//
// unsigned long MyFlashAddrCheckFunc(unsigned long ulAddr,
//                                    unsigned long ulSize);
//
//*****************************************************************************
//#define BL_FLASH_AD_CHECK_FN_HOOK MyFlashAddrCheckFunc

#endif // __BL_CONFIG_H__

//*****************************************************************************
//
// bl_emac.c - Functions to update via Ethernet.
//
// Copyright (c) 2013-2020 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// 
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package.
//
//*****************************************************************************

#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "bl_config.h"
#include "inc/hw_emac.h"
#include "inc/hw_flash.h"
#include "inc/hw_gpio.h"
#include "inc/hw_memmap.h"
#include "inc/hw_nvic.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/gpio.h"
#include "driverlib/pin_map.h"
#include "driverlib/emac.h"
#include "driverlib/sysctl.h"
#include "boot_loader/bl_decrypt.h"
#include "boot_loader/bl_flash.h"
#include "boot_loader/bl_hooks.h"
#include "driverlib/rom.h"
//
// Define ROM_SysCtlClockFreqSet() for snowflake RA0. Even though this function
// is deprecated in RA0 ROM, the function operates correctly when 
// SYSCTL_MOSCCTL register is configured correctly prior to calling this
// function.
//
#if defined(TARGET_IS_TM4C129_RA0)
#define ROM_SysCtlClockFreqSet                                                \
        ((uint32_t (*)(uint32_t ui32Config,                                   \
                       uint32_t ui32SysClock))ROM_SYSCTLTABLE[48])
#endif

//
// Define MAP_GPIOPadConfigSet() for the Boot Loader for Snowflake.
// This function fails in Snowflake for higher drive strengths, it will work
// properly for the instances where it is used here in the boot loader.
// 
#if defined(TARGET_IS_TM4C129_RA0) ||                                         \
    defined(TARGET_IS_TM4C129_RA1)
#define ROM_GPIOPadConfigSet                                                  \
        ((void (*)(uint32_t ui32Port,                                         \
                   uint8_t ui8Pins,                                           \
                   uint32_t ui32Strength,                                     \
                   uint32_t ui32PadType))ROM_GPIOTABLE[5])
#endif

//
// Define ROM_EMACInit for the bootloader of Snowflake RA0.  This function is
// deprecated in RA0 ROM, as it does not disable some interrupts that are not
// cleared by ***_EMACIntClear().  But that is not a problem for the bootloader
// as we are not enabling any interrupts.
//
#if defined(TARGET_IS_TM4C129_RA0)
#define ROM_EMACInit                                                          \
        ((void (*)(uint32_t ui32Base,                                         \
                   uint32_t ui32SysClk,                                       \
                   uint32_t ui32BusConfig,                                    \
                   uint32_t ui32RxBurst,                                      \
                   uint32_t ui32TxBurst,                                      \
                   uint32_t ui32DescSkipSize))ROM_EMACTABLE[8])
#endif

#include "driverlib/rom_map.h"

//*****************************************************************************
//
//! \addtogroup bl_emac_api
//! @{
//
//*****************************************************************************

#if defined(ENET_ENABLE_UPDATE) || defined(DOXYGEN)
//*****************************************************************************
//
// Make sure that the crystal frequency is defined.
//
//*****************************************************************************
#if !defined(CRYSTAL_FREQ)
#error ERROR: CRYSTAL_FREQ must be defined for Ethernet update!
#endif

//*****************************************************************************
//
// Make sure that boot loader update is not enabled (it is not supported via
// BOOTP given that there is no way to distinguish between a normal firmware
// image and a boot loader update image).
//
//*****************************************************************************
#if defined(ENABLE_BL_UPDATE)
#error ERROR: Updating the boot loader is not supported over Ethernet!
#endif

//*****************************************************************************
//
// TFTP packets contain 512 bytes of data and a packet shorter than this
// indicates the end of the transfer.
//
//*****************************************************************************
#define TFTP_BLOCK_SIZE         512

//*****************************************************************************
//
// uIP uses memset, so a simple one is provided here.  This is not as efficient
// as the one in the C library (from an execution time perspective), but it is
// much smaller.
//
//*****************************************************************************
void *
my_memset(void *pvDest, int iChar, size_t i32Length)
{
    int8_t *pi8Buf = (int8_t *)pvDest;

    //
    // Fill the buffer with the given character.
    //
    while(i32Length--)
    {
        *pi8Buf++ = iChar;
    }

    //
    // Return a pointer to the beginning of the buffer.
    //
    return(pvDest);
}

//*****************************************************************************
//
// uIP uses memcpy, so a simple one is provided here.  This is not as efficient
// as the one in the C library (from an execution time perspective), but it is
// much smaller.
//
//*****************************************************************************
void *
my_memcpy(void *pvDest, const void *pvSrc, size_t i32Length)
{
    const int8_t *pi8Src = (const int8_t *)pvSrc;
    int8_t *pi8Dest = (int8_t *)pvDest;

    //
    // Copy bytes from the source buffer to the destination buffer.
    //
    while(i32Length--)
    {
        *pi8Dest++ = *pi8Src++;
    }

    //
    // Return a pointer to the beginning of the destination buffer.
    //
    return(pvDest);
}

//*****************************************************************************
//
// Directly include the uIP code if using Ethernet for the update.  This allows
// non-Ethernet boot loader builds to not have to supply the uip-conf.h file
// that would otherwise be required.
//
//*****************************************************************************
#define memcpy my_memcpy
#define memset my_memset
#undef htonl
#undef ntohl
#undef htons
#undef ntohs
#include "third_party/uip-1.0/uip/pt.h"
#include "third_party/uip-1.0/uip/uip_arp.c"
#undef BUF
#include "third_party/uip-1.0/uip/uip.c"

//*****************************************************************************
//
// A prototype for the function (in the startup code) for a predictable length
// delay.
//
//*****************************************************************************
extern void Delay(uint32_t ui32Count);

//*****************************************************************************
//
// Defines for setting up the system clock.
//
//*****************************************************************************
#define SYSTICKHZ               100
#define SYSTICKMS               (1000 / SYSTICKHZ)

//*****************************************************************************
//
// UIP Timers (in ms)
//
//*****************************************************************************
#define UIP_PERIODIC_TIMER_MS   50
#define UIP_ARP_TIMER_MS        10000

//*****************************************************************************
//
// This structure defines the fields in a BOOTP request/reply packet.
//
//*****************************************************************************
typedef struct
{
    //
    // The operation; 1 is a request, 2 is a reply.
    //
    uint8_t ui8Op;

    //
    // The hardware type; 1 is Ethernet.
    //
    uint8_t ui8HType;

    //
    // The hardware address length; for Ethernet this will be 6, the length of
    // the MAC address.
    //
    uint8_t ui8HLen;

    //
    // Hop count, used by gateways for cross-gateway booting.
    //
    uint8_t ui8Hops;

    //
    // The transaction ID.
    //
    uint32_t ui32XID;

    //
    // The number of seconds elapsed since the client started trying to boot.
    //
    uint16_t ui16Secs;

    //
    // The BOOTP flags.
    //
    uint16_t ui16Flags;

    //
    // The client's IP address, if it knows it.
    //
    uint32_t ui32CIAddr;

    //
    // The client's IP address, as assigned by the BOOTP server.
    //
    uint32_t ui32YIAddr;

    //
    // The TFTP server's IP address.
    //
    uint32_t ui32SIAddr;

    //
    // The gateway IP address, if booting cross-gateway.
    //
    uint32_t ui32GIAddr;

    //
    // The hardware address; for Ethernet this is the MAC address.
    //
    uint8_t pui8CHAddr[16];

    //
    // The name, or nickname, of the server that should handle this BOOTP
    // request.
    //
    char pcSName[64];

    //
    // The name of the boot file to be loaded via TFTP.
    //
    char pcFile[128];

    //
    // Optional vendor-specific area; not used for BOOTP.
    //
    uint8_t pui8Vend[64];
}
tBOOTPPacket;

//*****************************************************************************
//
// The BOOTP commands.
//
//*****************************************************************************
#define BOOTP_REQUEST           1
#define BOOTP_REPLY             2

//*****************************************************************************
//
// The TFTP commands.
//
//*****************************************************************************
#define TFTP_RRQ                1
#define TFTP_WRQ                2
#define TFTP_DATA               3
#define TFTP_ACK                4
#define TFTP_ERROR              5

//*****************************************************************************
//
// The UDP ports used by the BOOTP protocol.
//
//*****************************************************************************
#define BOOTP_SERVER_PORT       67
#define BOOTP_CLIENT_PORT       68

//*****************************************************************************
//
// The UDP port for the TFTP server.
//
//*****************************************************************************
#define TFTP_PORT               69

//*****************************************************************************
//
// The MAC address of the Ethernet interface.
//
//*****************************************************************************
#ifdef ENET_MAC_ADDR0
static struct uip_eth_addr g_sMACAddr =
{
    {
        ENET_MAC_ADDR0,
        ENET_MAC_ADDR1,
        ENET_MAC_ADDR2,
        ENET_MAC_ADDR3,
        ENET_MAC_ADDR4,
        ENET_MAC_ADDR5
    }
};
#else
static struct uip_eth_addr g_sMACAddr;
#endif

//*****************************************************************************
//
// The number of SysTick interrupts since the start of the boot loader.
//
//*****************************************************************************
static uint32_t g_ui32Ticks;

//*****************************************************************************
//
// The seed for the random number generator.
//
//*****************************************************************************
static uint32_t g_ui32RandomSeed;

//*****************************************************************************
//
// The number of milliseconds since the last call to uip_udp_periodic().
//
//*****************************************************************************
static volatile uint32_t g_ui32PeriodicTimer;

//*****************************************************************************
//
// The number of milliseconds since the last call to uip_arp_timer().
//
//*****************************************************************************
static volatile uint32_t g_ui32ARPTimer;

//*****************************************************************************
//
// The transaction ID of the most recently sent out BOOTP request.
//
//*****************************************************************************
static uint32_t g_ui32XID;

//*****************************************************************************
//
// The state for the proto-thread that handles the BOOTP process.
//
//*****************************************************************************
static struct pt g_sThread;

//*****************************************************************************
//
// The amount of time to wait for a BOOTP reply before sending out a new BOOTP
// request.
//
//*****************************************************************************
static uint32_t g_ui32Delay;

//*****************************************************************************
//
// The target time (relative to g_ui32Ticks) when the next timeout occurs.
//
//*****************************************************************************
static uint32_t g_ui32Target;

//*****************************************************************************
//
// The IP address of the TFTP server.
//
//*****************************************************************************
static uip_ipaddr_t g_sServerAddr;

//*****************************************************************************
//
// The name of the file to be read from the TFTP server.
//
//*****************************************************************************
static char g_pcFilename[128];

//*****************************************************************************
//
// The end of flash.  If there is not a reserved block at the end of flash,
// this is the real end of flash.  If there is a reserved block, this is the
// start of the reserved block (i.e. the virtual end of flash).
//
//*****************************************************************************
static uint32_t g_ui32FlashEnd;

//*****************************************************************************
//
// The current block being read from the TFTP server.
//
//*****************************************************************************
static uint32_t g_ui32TFTPBlock;

//*****************************************************************************
//
// The number of TFTP retries.
//
//*****************************************************************************
static uint32_t g_ui32TFTPRetries;

//*****************************************************************************
//
// The UDP socket used to communicate with the BOOTP and TFTP servers (in
// sequence).
//
//*****************************************************************************
struct uip_udp_conn *g_pConn;

//*****************************************************************************
//
// The current link status.
//
//*****************************************************************************
static uint32_t g_ui32Link;

//*****************************************************************************
//
// Ethernet DMA descriptors.
//
// Although uIP uses a single buffer, the MAC hardware needs a minimum of
// 3 receive descriptors to operate.
//
//*****************************************************************************
#define NUM_TX_DESCRIPTORS 3
#define NUM_RX_DESCRIPTORS 3
tEMACDMADescriptor g_psRxDescriptor[NUM_TX_DESCRIPTORS];
tEMACDMADescriptor g_psTxDescriptor[NUM_RX_DESCRIPTORS];
uint32_t g_ui32RxDescIndex;
uint32_t g_ui32TxDescIndex;

//*****************************************************************************
//
// Transmit and receive buffers.
//
//*****************************************************************************
#define RX_BUFFER_SIZE 1536
#define TX_BUFFER_SIZE 1536
uint8_t g_pui8RxBuffer[RX_BUFFER_SIZE];
uint8_t g_pui8TxBuffer[TX_BUFFER_SIZE];

//*****************************************************************************
//
//! Handles the SysTick interrupt.
//!
//! This function is called when the SysTick interrupt occurs.  It simply
//! keeps a running count of interrupts, used as a time basis for the BOOTP and
//! TFTP protocols.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntHandler(void)
{
    //
    // Increment the tick count.
    //
    g_ui32Ticks++;
    g_ui32PeriodicTimer += SYSTICKMS;
    g_ui32ARPTimer += SYSTICKMS;
}

//*****************************************************************************
//
//! Computes a new random number.
//!
//! This function computes a new pseudo-random number, using a linear
//! congruence random number generator.  Note that if the entire 32-bits of the
//! produced random number are not being used, the upper N bits should be used
//! instead of the lower N bits as they are much more random (for example, use
//! ``RandomNumber() >> 28'' instead of ``RandomNumber() & 15'').
//!
//! \return Returns a 32-bit pseudo-random number.
//
//*****************************************************************************
static uint32_t
RandomNumber(void)
{
    //
    // Generate a new pseudo-random number with a linear congruence random
    // number generator.  This new random number becomes the seed for the next
    // random number.
    //
    g_ui32RandomSeed = (g_ui32RandomSeed * 1664525) + 1013904223;

    //
    // Return the new random number.
    //
    return(g_ui32RandomSeed);
}

//*****************************************************************************
//
// Read a packet from the DMA receive buffer into the uIP packet buffer.
//
//*****************************************************************************
static int32_t
PacketReceive(uint8_t *pui8Buf, int32_t i32BufLen)
{
    int_fast32_t i32FrameLen, i32Loop;

    //
    // By default, we assume we got a bad frame.
    //
    i32FrameLen = 0;

    //
    // See if the receive descriptor contains a valid frame.  Look for a
    // descriptor error, indicating that the incoming packet was truncated or,
    // if this is the last frame in a packet, the receive error bit.
    //
    if(!(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &
         DES0_RX_STAT_ERR))
    {
        //
        // We have a valid frame so copy the content to the supplied buffer.
        // First check that the "last descriptor" flag is set.  We sized the
        // receive buffer such that it can always hold a valid frame so this
        // flag should never be clear at this point but...
        //
        if(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &
           DES0_RX_STAT_LAST_DESC)
        {
            i32FrameLen =
                ((g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &
                  DES0_RX_STAT_FRAME_LENGTH_M) >>
                 DES0_RX_STAT_FRAME_LENGTH_S);

            //
            // Sanity check.  This shouldn't be required since we sized the uIP
            // buffer such that it's the same size as the DMA receive buffer
            // but, just in case...
            //
            if(i32FrameLen > i32BufLen)
            {
                i32FrameLen = i32BufLen;
            }

            //
            // Copy the data from the DMA receive buffer into the provided
            // frame buffer.
            //
            for(i32Loop = 0; i32Loop < i32FrameLen; i32Loop++)
            {
                pui8Buf[i32Loop] = g_pui8RxBuffer[i32Loop];
            }
        }
    }

    //
    // Move on to the next descriptor in the chain.
    //
    g_ui32RxDescIndex++;
    if(g_ui32RxDescIndex == NUM_RX_DESCRIPTORS)
    {
        g_ui32RxDescIndex = 0;
    }

    //
    // Mark the next descriptor in the ring as available for the receiver to
    // write into.
    //
    g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus = DES0_RX_CTRL_OWN;

    //
    // Return the Frame Length
    //
    return(i32FrameLen);
}

//*****************************************************************************
//
// Transmit a packet from the supplied buffer.
//
//*****************************************************************************
static int32_t
PacketTransmit(uint8_t *pui8Buf, int32_t i32BufLen)
{
    int_fast32_t i32Loop;

    //
    // Wait for the previous packet to be transmitted.
    //
    while(g_psTxDescriptor[g_ui32TxDescIndex].ui32CtrlStatus &
          DES0_TX_CTRL_OWN)
    {
    }

    //
    // Check that we're not going to overflow the transmit buffer.  This
    // shouldn't be necessary since the uIP buffer is smaller than our DMA
    // transmit buffer but, just in case...
    //
    if(i32BufLen > TX_BUFFER_SIZE)
    {
        i32BufLen = TX_BUFFER_SIZE;
    }

    //
    // Copy the packet data into the transmit buffer.
    //
    for(i32Loop = 0; i32Loop < i32BufLen; i32Loop++)
    {
        g_pui8TxBuffer[i32Loop] = pui8Buf[i32Loop];
    }

    //
    // Move to the next descriptor.
    //
    g_ui32TxDescIndex++;
    if(g_ui32TxDescIndex == NUM_TX_DESCRIPTORS)
    {
        g_ui32TxDescIndex = 0;
    }

    //
    // Fill in the packet size and tell the transmitter to start work.
    //
    g_psTxDescriptor[g_ui32TxDescIndex].ui32Count = (uint32_t)i32BufLen;
    g_psTxDescriptor[g_ui32TxDescIndex].ui32CtrlStatus =
        (DES0_TX_CTRL_LAST_SEG | DES0_TX_CTRL_FIRST_SEG |
         DES0_TX_CTRL_INTERRUPT | DES0_TX_CTRL_IP_ALL_CKHSUMS |
         DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_OWN);

    //
    // Tell the DMA to reacquire the descriptor now that we've filled it in.
    //
    ROM_EMACTxDMAPollDemand(EMAC0_BASE);

    //
    // Return the number of bytes sent.
    //
    return(i32BufLen);
}

//*****************************************************************************
//
//! Constructs and sends a BOOTP request packet.
//!
//! This function constructs a BOOTP request packet and sends it as a broadcast
//! message to the network.
//!
//! \return None.
//
//*****************************************************************************
static void
SendBOOTPRequest(void)
{
    uint8_t *pui8Packet = (uint8_t *)uip_appdata;
    tBOOTPPacket *psBOOTP = (tBOOTPPacket *)uip_appdata;
    uint32_t ui32Idx;

    //
    // Zero fill the BOOTP request packet.
    //
    for(ui32Idx = 0; ui32Idx < sizeof(tBOOTPPacket); ui32Idx++)
    {
        pui8Packet[ui32Idx] = 0;
    }

    //
    // Construct a BOOTP request.
    //
    psBOOTP->ui8Op = BOOTP_REQUEST;

    //
    // Set the hardware type to Ethernet.
    //
    psBOOTP->ui8HType = 0x01;

    //
    // Set the hardware address length to 6.
    //
    psBOOTP->ui8HLen = 0x06;

    //
    // Choose a random number for the transaction ID.
    //
    psBOOTP->ui32XID = g_ui32XID = RandomNumber();

    //
    // Set the number of seconds since we started.
    //
    psBOOTP->ui16Secs = HTONS(g_ui32Ticks / SYSTICKHZ);

    //
    // Fill in the Ethernet MAC address.
    //
    for(ui32Idx = 0; ui32Idx < 6; ui32Idx++)
    {
        psBOOTP->pui8CHAddr[ui32Idx] = g_sMACAddr.addr[ui32Idx];
    }

    //
    // Set the server name if defined.
    //
#ifdef ENET_BOOTP_SERVER
    for(ui32Idx = 0;
        (psBOOTP->pcSName[ui32Idx] = ENET_BOOTP_SERVER[ui32Idx]) != 0;
        ui32Idx++)
    {
    }
#endif

    //
    // Send the BOOTP request packet.
    //
    uip_udp_send(sizeof(tBOOTPPacket));
}

//*****************************************************************************
//
//! Parses a packet checking for a BOOTP reply message.
//!
//! This function parses a packet to determine if it is a BOOTP reply to our
//! currently outstanding BOOTP request.  If a valid reply is found, the
//! appropriate information from the packet is extracted and saved.
//!
//! \return Returns 1 if a valid BOOTP reply message was found and 0 otherwise.
//
//*****************************************************************************
static uint32_t
ParseBOOTPReply(void)
{
    tBOOTPPacket *psBOOTP = (tBOOTPPacket *)uip_appdata;
    uint32_t ui32Idx;

    //
    // See if this is a reply for our current BOOTP request.
    //
    if((psBOOTP->ui8Op != BOOTP_REPLY) ||
       (psBOOTP->ui32XID != g_ui32XID) ||
       (*(uint32_t *)psBOOTP->pui8CHAddr != *(uint32_t *)g_sMACAddr.addr) ||
       (*(uint16_t *)(psBOOTP->pui8CHAddr + 4) !=
        *(uint16_t *)(g_sMACAddr.addr + 4)))
    {
        return(0);
    }

    //
    // Extract our IP address from the response.
    //
    *((uint32_t *)(void *)(&uip_hostaddr)) = psBOOTP->ui32YIAddr;

    //
    // Extract the server address from the response.
    //
    *((uint32_t *)(void *)(&g_sServerAddr)) = psBOOTP->ui32SIAddr;

    //
    // Save the boot file name.
    //
    for(ui32Idx = 0;
        ((g_pcFilename[ui32Idx] = psBOOTP->pcFile[ui32Idx]) != 0) &&
        (ui32Idx < (sizeof(g_pcFilename) - 1));
        ui32Idx++)
    {
    }
    g_pcFilename[ui32Idx] = 0;

    //
    // A valid BOOTP reply was found and decoded.
    //
    return(1);
}


//*****************************************************************************
//
//! Constructs and sends a TFTP error packet.
//!
//! This function constructs a TFTP read request packet (RRQ) and sends it to
//! the server.
//!
//! \return None.
//
//*****************************************************************************
static void
SendTFTPError(uint16_t ui16Error, char *pcString)
{
    uint8_t *pui8Packet = (uint8_t *)uip_appdata;
    int32_t i32Len;

    pui8Packet[0] = (TFTP_ERROR >> 8) & 0xff;
    pui8Packet[1] = TFTP_ERROR & 0xff;
    pui8Packet[2] = (ui16Error >> 8) & 0xFF;
    pui8Packet[3] = ui16Error & 0xFF;

    //
    // Get ready to copy the error string.
    //
    i32Len = 4;
    pui8Packet += 4;

    //
    // Copy as much of the string as we can fit.
    //
    while((i32Len < (UIP_APPDATA_SIZE - 1)) && *pcString)
    {
        *pui8Packet++ = *pcString++;
        i32Len++;
    }

    //
    // Write the terminating 0.
    //
    *pui8Packet = (uint8_t)0;

    //
    // Send the error packet.
    //
    uip_udp_send(i32Len + 1);
}

//*****************************************************************************
//
//! Constructs and sends a TFTP read packet.
//!
//! This function constructs a TFTP read request packet (RRQ) and sends it to
//! the server.
//!
//! \return None.
//
//*****************************************************************************
static void
SendTFTPGet(void)
{
    uint8_t *pui8Packet = (uint8_t *)uip_appdata;
    uint32_t ui32Idx;
    char *pcFilename;

    //
    // The TFTP RRQ packet should be sent to the TFTP server port.
    //
    g_pConn->rport = HTONS(TFTP_PORT);

    //
    // Set the TFTP packet opcode to RRQ.
    //
    pui8Packet[0] = (TFTP_RRQ >> 8) & 0xff;
    pui8Packet[1] = TFTP_RRQ & 0xff;

    //
    // Copy the file name into the RRQ packet.
    //
    for(ui32Idx = 2, pcFilename = g_pcFilename;
        (pui8Packet[ui32Idx++] = *pcFilename++) != 0; )
    {
    }

    //
    // Set the transfer mode to binary.
    //
    for(pcFilename = "octet"; (pui8Packet[ui32Idx++] = *pcFilename++) != 0; )
    {
    }

    //
    // Send the TFTP read packet.
    //
    uip_udp_send(ui32Idx);
}

//*****************************************************************************
//
//! Parses a packet checking for a TFTP data packet.
//!
//! This function parses a packet to determine if it is a TFTP data packet for
//! a current TFTP transfer.  If a valid packet is found, the contents of the
//! packet are programmed into flash.
//!
//! \return Returns 1 if this packet was the last packet of the TFTP data
//! transfer and 0 otherwise.
//
//*****************************************************************************
static uint32_t
ParseTFTPData(void)
{
    uint8_t *pui8Packet = (uint8_t *)uip_appdata;
    uint32_t ui32FlashAddr;
    uint32_t ui32Idx;

    //
    // See if this is a TFTP data packet.
    //
    if((pui8Packet[0] != ((TFTP_DATA >> 8) && 0xff)) ||
       (pui8Packet[1] != (TFTP_DATA & 0xff)))
    {
        return(0);
    }

    //
    // If the remote port on our connection is still the TFTP server port (i.e.
    // this is the first data packet), then copy the transaction ID for the
    // TFTP data connection into our connection.  This will ensure that our
    // response will be sent to the correct port.
    //
    if(g_pConn->rport == HTONS(TFTP_PORT))
    {
        g_pConn->rport =
            ((struct uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN])->srcport;
    }

    //
    // See if this is the correct data packet.
    //
    if((pui8Packet[2] != ((g_ui32TFTPBlock >> 8) & 0xff)) ||
       (pui8Packet[3] != (g_ui32TFTPBlock & 0xff)))
    {
        //
        // Since the wrong data packet was sent, resend the ACK for it since
        // we've already processed it.
        //
        pui8Packet[0] = (TFTP_ACK >> 8) & 0xff;
        pui8Packet[1] = TFTP_ACK & 0xff;
        uip_udp_send(4);

        //
        // Ignore this packet.
        //
        return(0);
    }

    //
    // What address are we about to program to?
    //
    ui32FlashAddr =
        ((g_ui32TFTPBlock - 1) * TFTP_BLOCK_SIZE) + APP_START_ADDRESS;

    //
    // Do not program this data into flash if it is beyond the end of flash.
    //
    if(ui32FlashAddr < g_ui32FlashEnd)
    {
        //
        // If this is the first block and we have been provided with a start
        // hook function, call it here to indicate that we are about to begin
        // flashing a new image.
        //
#ifdef BL_START_FN_HOOK
        if(g_ui32TFTPBlock == 1)
        {
            BL_START_FN_HOOK();
        }
#endif

        //
        // Clear any flash error indicator.
        //
        BL_FLASH_CL_ERR_FN_HOOK();

        //
        // If this is the first data packet and code protection is enabled,
        // then erase the entire flash.
        //
#ifdef FLASH_CODE_PROTECTION
        if(g_ui32TFTPBlock == 1)
        {
            //
            // Loop through the pages in the flash, excluding the pages that
            // contain the boot loader and the optional reserved space.
            //
            for(ui32Idx = APP_START_ADDRESS; ui32Idx < g_ui32FlashEnd;
                ui32Idx += FLASH_PAGE_SIZE)
            {
                //
                // Erase this block of the flash.
                //
                BL_FLASH_ERASE_FN_HOOK((ui32Idx);
            }
        }
#else
        //
        // Flash code protection is not enabled, so see if the data in this
        // packet will be programmed to the beginning of a flash block.  We
        // assume that the flash block size is always a multiple of 1KB so,
        // since each TFTP packet is 512 bytes and that the start must always
        // be on a flash page boundary, we can be sure that we will hit the
        // start of each page as we receive packets.
        //
        if(!(ui32FlashAddr & (FLASH_PAGE_SIZE - 1)))
        {
            //
            // Erase this block of the flash.
            //
            BL_FLASH_ERASE_FN_HOOK(ui32FlashAddr);
        }
#endif

        //
        // Decrypt the data if required.
        //
#ifdef BL_DECRYPT_FN_HOOK
        BL_DECRYPT_FN_HOOK(pui8Packet + 4, uip_len - 4);
#endif

        //
        // Program this block of data into flash.
        //
        BL_FLASH_PROGRAM_FN_HOOK(ui32FlashAddr, (pui8Packet + 4),
                                 (uip_len - 4));

        //
        // If a progress reporting hook function has been provided, call it
        // here.  The TFTP protocol doesn't let us know how large the image is
        // before it starts the transfer so we pass 0 as the ui32Total
        // parameter to indicate this.
        //
#ifdef BL_PROGRESS_FN_HOOK
        BL_PROGRESS_FN_HOOK(((ui32FlashAddr - APP_START_ADDRESS) +
                             (uip_len - 4)), 0);
#endif
    }

    //
    // Increment to the next block.
    //
    g_ui32TFTPBlock++;

    //
    // Save the packet length.
    //
    ui32Idx = uip_len;

    //
    // Did we see any error?
    //
    if(BL_FLASH_ERROR_FN_HOOK())
    {
        //
        // Yes - send back an error packet.
        //
        SendTFTPError(2, "Error programming flash.");
    }
    else
    {
        //
        // No errors reported so construct an ACK packet.  The block number
        // field is already correct, so it does not need to be set.
        //
        pui8Packet[0] = (TFTP_ACK >> 8) & 0xff;
        pui8Packet[1] = TFTP_ACK & 0xff;

        //
        // Send the ACK packet to the TFTP server.
        //
        uip_udp_send(4);
    }

    //
    // If the packet was shorter than TFTP_BLOCK_SIZE bytes then this was the
    // last packet in the file.
    //
    if(ui32Idx != (TFTP_BLOCK_SIZE + 4))
    {
        //
        // If an end signal hook function has been provided, call it here.
        //
#ifdef BL_END_FN_HOOK
        BL_END_FN_HOOK();
#endif
        return(1);
    }
    //
    // There is more data to be read.
    //
    return(0);
}

uint16_t
LOCAL_EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
{

    //
    // Make sure the MII is idle.
    //
    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
    {
    }

    //
    // Tell the MAC to read the given PHY register.
    //
    HWREG(ui32Base + EMAC_O_MIIADDR) =
        ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
         (ui8RegAddr << EMAC_MIIADDR_MII_S) |
         (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);

    //
    // Wait for the read to complete.
    //
    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
    {
    }

    //
    // Return the result.
    //
    return(HWREG(ui32Base + EMAC_O_MIIDATA) & EMAC_MIIDATA_DATA_M);
}

//*****************************************************************************
//
//! Handles the BOOTP process.
//!
//! This function contains the proto-thread for handling the BOOTP process.  It
//! first communicates with the BOOTP server to get its boot parameters (IP
//! address, server address, and file name), then it communicates with the TFTP
//! server on the specified server to read the firmware image file.
//!
//! \return None.
//
//*****************************************************************************
#ifdef DOXYGEN
char
BOOTPThread(void)
#else
PT_THREAD(BOOTPThread(void))
#endif
{
    //
    // Begin the proto-thread.
    //
    PT_BEGIN(&g_sThread);

wait_for_link:
    PT_WAIT_UNTIL(&g_sThread,
                  (LOCAL_EMACPHYRead(EMAC0_BASE, 0, EPHY_BMSR) &
                   EPHY_BMSR_LINKSTAT) != 0);

    //
    // Reset the host address.
    //
    *((uint32_t *)(void *)(&uip_hostaddr)) = 0;

    //
    // Re-bind the UDP socket for sending requests to the BOOTP server.
    //
    uip_udp_remove(g_pConn);
    *((uint32_t *)(void *)(&g_sServerAddr)) = 0xffffffff;
    uip_udp_new(&g_sServerAddr, HTONS(BOOTP_SERVER_PORT));
    uip_udp_bind(g_pConn, HTONS(BOOTP_CLIENT_PORT));

    //
    // Set the initial delay between BOOTP requests to 1 second.
    //
    g_ui32Delay = SYSTICKHZ;

    //
    // Loop forever.  This loop is explicitly exited when a valid BOOTP reply
    // is received.
    //
    while(1)
    {
        //
        // Send a BOOTP request.
        //
        SendBOOTPRequest();

        //
        // Set the amount of time to wait for the BOOTP reply message.
        //
        g_ui32Target = g_ui32Ticks + g_ui32Delay;

        //
        // Wait until a packet is received or the timeout has occurred.
        //
wait_for_bootp_reply:
        PT_WAIT_UNTIL(&g_sThread,
                      ((g_ui32Link = (LOCAL_EMACPHYRead(EMAC0_BASE, 0, EPHY_BMSR) &
                                      EPHY_BMSR_LINKSTAT)) == 0) ||
                      uip_newdata() || (g_ui32Ticks > g_ui32Target));

        //
        // If the link has been lost, go back to waiting for a link.
        //
        if(g_ui32Link == 0)
        {
            goto wait_for_link;
        }
                      
        //
        // See if a packet has been received.
        //
        if(uip_newdata())
        {
            //
            // Clear the new data flag so that this packet will only be
            // examined one time.
            //
            uip_flags &= ~(UIP_NEWDATA);

            //
            // See if this is a BOOTP reply.
            //
            if(ParseBOOTPReply() == 1)
            {
                break;
            }

            //
            // This was not a BOOTP reply packet, so go back to waiting.
            //
            goto wait_for_bootp_reply;
        }

        //
        // If the delay between BOOTP requests is less than 60 seconds, double
        // the delay time.  This avoids constantly slamming the network with
        // requests.
        //
        if(g_ui32Delay < (60 * SYSTICKHZ))
        {
            g_ui32Delay *= 2;
        }
    }

    //
    // Reconfigure the UDP socket to target the TFTP port on the server.
    //
    uip_ipaddr_copy(&g_pConn->ripaddr, g_sServerAddr);
    uip_udp_bind(g_pConn, HTONS(13633));

    //
    // Send a TFTP read request.
    //
    SendTFTPGet();

    //
    // Since the first TFTP read request will result in an ARP request, delay
    // for just a bit and then re-issue the TFTP read request.
    //
    PT_YIELD(&g_sThread);

    //
    // Resend the TFTP read request.  If the ARP request has already been
    // answered, this will go out as is and avoid the two second timeout below.
    //
    SendTFTPGet();

    //
    // Start the TFTP transfer from block one.
    //
    g_ui32TFTPBlock = 1;

    //
    // Set the number of TFTP retries to zero.
    //
    g_ui32TFTPRetries = 0;

    //
    // Loop forever.  This loop is explicitly exited when the TFTP transfer has
    // completed.
    //
    while(1)
    {
        //
        // Set the amount of time to wait for the TFTP data packet.
        //
        g_ui32Target = g_ui32Ticks + (SYSTICKHZ * 4);

        //
        // Wait until a packet is received or the timeout has occurred.
        //
        PT_WAIT_UNTIL(&g_sThread,
                      ((g_ui32Link = (LOCAL_EMACPHYRead(EMAC0_BASE, 0, EPHY_BMSR) &
                                      EPHY_BMSR_LINKSTAT)) == 0) ||
                      uip_newdata() || (g_ui32Ticks > g_ui32Target));

        //
        // If the link has been lost, go back to waiting for a link.
        //
        if(g_ui32Link == 0)
        {
            goto wait_for_link;
        }
                      
        //
        // See if a packet has been received.
        //
        if(uip_newdata())
        {
            //
            // Clear the new data flag so that this packet will only be
            // examined one time.
            //
            uip_flags &= ~(UIP_NEWDATA);

            //
            // See if this is a TFTP data packet.
            //
            if(ParseTFTPData() == 1)
            {
                break;
            }
        }
        else if(g_ui32TFTPRetries < 3)
        {
            //
            // The transfer timed out, so send a new TFTP read request.
            //
            SendTFTPGet();

            //
            // Start the TFTP transfer from block one.
            //
            g_ui32TFTPBlock = 1;

            //
            // Increment the count of TFTP retries.
            //
            g_ui32TFTPRetries++;
        }
        else
        {
            //
            // The TFTP transfer failed after three retries, so start over.
            //
            goto wait_for_link;
        }
    }
    //
    // Wait for the last packet to be transmitted.
    //
    while(g_psTxDescriptor[g_ui32TxDescIndex].ui32CtrlStatus &
          DES0_TX_CTRL_OWN)
    {
    }

    //
    // Wait for a bit to make sure that the final ACK packet is transmitted.
    //
    g_ui32Target = g_ui32Ticks + (SYSTICKHZ / 4);
    while(g_ui32Ticks < g_ui32Target)
    {
        PT_YIELD(&g_sThread);
    }

    //
    // Perform a software reset request.  This will cause the microcontroller
    // to reset; no further code will be executed.
    //
    HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;

    //
    // The microcontroller should have reset, so this should never be reached.
    // Just in case, loop forever.
    //
    while(1)
    {
    }

    //
    // End the proto-thread.
    //
    PT_END(&g_sThread);
}

static void
LOCAL_EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config)
{
    //
    // Write the Ethernet PHY configuration to the peripheral configuration
    // register.
    //
    HWREG(ui32Base + EMAC_O_PC) = ui32Config;

    //
    // If using the internal PHY, reset it to ensure that new configuration is
    // latched there.
    //
    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL)
    {
        ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
        while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0))
        {
            //
            // Wait for the PHY reset to complete.
            //
        }

        //
        // Delay a bit longer to ensure that the PHY reset has completed.
        //
        ROM_SysCtlDelay(1000);
    }

    //
    // If using an external RMII PHY, we must set 2 bits in the Ethernet MAC
    // Clock Configuration Register.
    //
    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_EXTERNAL_RMII)
    {
        //
        // Select and enable the external clock from the RMII PHY.
        //
        HWREG(EMAC0_BASE + EMAC_O_CC) |= EMAC_CC_CLKEN;
    }
    else
    {
        //
        // Disable the external clock.
        //
        HWREG(EMAC0_BASE + EMAC_O_CC) &= ~EMAC_CC_CLKEN;
    }

    //
    // Reset the MAC regardless of whether the PHY connection changed or not.
    //
    ROM_EMACReset(EMAC0_BASE);

    ROM_SysCtlDelay(1000);
}

//*****************************************************************************
//
//! Reconfigures the Ethernet controller.
//!
//! \param ui32Clock is the system clock frequency.
//!
//! This function reconfigures the Ethernet controller, preparing it for use by
//! the boot loader.  This performs the steps common between the direct
//! invocation of the boot loader and the application invocation of the boot
//! loader.
//!
//! \return None.
//
//*****************************************************************************
void
EnetReconfig(uint32_t ui32Clock)
{
    uip_ipaddr_t sAddr;
    uint32_t ui32Loop;
    uint32_t ui32User0, ui32User1;

    //
    // Configure for use with the internal PHY.
    //
    LOCAL_EMACPHYConfigSet(EMAC0_BASE,
                           (EMAC_PHY_TYPE_INTERNAL | EMAC_PHY_INT_MDIX_EN |
                            EMAC_PHY_AN_100B_T_FULL_DUPLEX));
    

    //
    // Reset the MAC.
    //
    ROM_EMACReset(EMAC0_BASE);

    //
    // Initialize the MAC and set the DMA mode.
    //
    ROM_EMACInit(EMAC0_BASE, ui32Clock,
             EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED, 4, 4, 0);

    //
    // Get the MAC address from the flash user registers.  If it has not been
    // programmed, then use the boot loader default MAC address.
    //
    ROM_FlashUserGet(&ui32User0, &ui32User1);
    if((ui32User0 == 0xffffffff) || (ui32User1 == 0xffffffff))
    {
        //
        // MAC address has not been programmed, use default.
        //
        g_sMACAddr.addr[0] = 0x00;
        g_sMACAddr.addr[1] = 0x1a;
        g_sMACAddr.addr[2] = 0xb6;
        g_sMACAddr.addr[3] = 0x00;
        g_sMACAddr.addr[4] = 0x64;
        g_sMACAddr.addr[5] = 0x00;
    }
    else
    {
        g_sMACAddr.addr[0] = ui32User0 & 0xff;
        g_sMACAddr.addr[1] = (ui32User0 >> 8) & 0xff;
        g_sMACAddr.addr[2] = (ui32User0 >> 16) & 0xff;
        g_sMACAddr.addr[3] = ui32User1 & 0xff;
        g_sMACAddr.addr[4] = (ui32User1 >> 8) & 0xff;
        g_sMACAddr.addr[5] = (ui32User1 >> 16) & 0xff;
    }

    //
    // Set MAC configuration options.
    //
    ROM_EMACConfigSet(EMAC0_BASE,
                  (EMAC_CONFIG_FULL_DUPLEX | EMAC_CONFIG_CHECKSUM_OFFLOAD |
                   EMAC_CONFIG_7BYTE_PREAMBLE | EMAC_CONFIG_IF_GAP_96BITS |
                   EMAC_CONFIG_USE_MACADDR0 | EMAC_CONFIG_SA_FROM_DESCRIPTOR |
                   EMAC_CONFIG_BO_LIMIT_1024),
                  (EMAC_MODE_RX_STORE_FORWARD | EMAC_MODE_TX_STORE_FORWARD |
                   EMAC_MODE_TX_THRESHOLD_64_BYTES |
                   EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);

    //
    // Initialize each of the transmit descriptors.  Note that we leave the OWN
    // bit clear here since we have not set up any transmissions yet.
    //
    for(ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++)
    {
        g_psTxDescriptor[ui32Loop].ui32Count =
            (DES1_TX_CTRL_SADDR_INSERT |
             (TX_BUFFER_SIZE << DES1_TX_CTRL_BUFF1_SIZE_S));
        g_psTxDescriptor[ui32Loop].pvBuffer1 = g_pui8TxBuffer;
        g_psTxDescriptor[ui32Loop].DES3.pLink =
            (ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ?
            g_psTxDescriptor : &g_psTxDescriptor[ui32Loop + 1];
        g_psTxDescriptor[ui32Loop].ui32CtrlStatus =
            (DES0_TX_CTRL_LAST_SEG | DES0_TX_CTRL_FIRST_SEG |
             DES0_TX_CTRL_INTERRUPT | DES0_TX_CTRL_CHAINED |
             DES0_TX_CTRL_IP_ALL_CKHSUMS);
    }

    //
    // Initialize each of the receive descriptors.  We clear the OWN bit here
    // to make sure that the receiver doesn't start writing anything
    // immediately.
    //
    for(ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++)
    {
        g_psRxDescriptor[ui32Loop].ui32CtrlStatus = 0;
        g_psRxDescriptor[ui32Loop].ui32Count =
            (DES1_RX_CTRL_CHAINED |
             (RX_BUFFER_SIZE << DES1_RX_CTRL_BUFF1_SIZE_S));
        g_psRxDescriptor[ui32Loop].pvBuffer1 = g_pui8RxBuffer;
        g_psRxDescriptor[ui32Loop].DES3.pLink =
            (ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ?
            g_psRxDescriptor : &g_psRxDescriptor[ui32Loop + 1];
    }

    //
    // Set the descriptor pointers in the hardware.
    //
    ROM_EMACRxDMADescriptorListSet(EMAC0_BASE, g_psRxDescriptor);
    ROM_EMACTxDMADescriptorListSet(EMAC0_BASE, g_psTxDescriptor);

    //
    // Start from the beginning of both descriptor chains.  We actually set
    // the transmit descriptor index to the last descriptor in the chain
    // since it will be incremented before use and this means the first
    // transmission we perform will use the correct descriptor.
    //
    g_ui32RxDescIndex = 0;
    g_ui32TxDescIndex = NUM_TX_DESCRIPTORS - 1;

    //
    // Program the MAC address.
    //
    ROM_EMACAddrSet(EMAC0_BASE, 0, g_sMACAddr.addr);

    //
    // Wait for the link to become active.
    //
    while((ROM_EMACPHYRead(EMAC0_BASE, 0, EPHY_BMSR) &
           EPHY_BMSR_LINKSTAT) == 0)
    {
    }

    //
    // Set MAC filtering options.  We receive all broadcast and multicast
    // packets along with those addressed specifically for us.
    //
    ROM_EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_SADDR |
                                    EMAC_FRMFILTER_PASS_MULTICAST |
                                    EMAC_FRMFILTER_PASS_NO_CTRL));

    //
    // Seed the random number generator from the MAC address.
    //
    g_ui32RandomSeed = *(uint32_t *)(g_sMACAddr.addr + 2);

    //
    // Initialize the uIP stack.
    //
    uip_init();
    uip_arp_init();

    //
    // Set the MAC address.
    //
    uip_setethaddr(g_sMACAddr);

    //
    // Initialize the proto-thread used by the BOOTP protocol handler.
    //
    PT_INIT(&g_sThread);

    //
    // Create a UDP socket for sending requests to the BOOTP server.  After the
    // BOOTP portion of the protocol has been handled, this socket will be
    // reused to communicate with the TFTP server.
    //
    *((uint32_t *)(void *)(&sAddr)) = 0xffffffff;
    g_pConn = uip_udp_new(&sAddr, HTONS(BOOTP_SERVER_PORT));
    uip_udp_bind(g_pConn, HTONS(BOOTP_CLIENT_PORT));

    //
    // Enable the Ethernet MAC transmitter and receiver.
    //
    ROM_EMACTxEnable(EMAC0_BASE);
    ROM_EMACRxEnable(EMAC0_BASE);

    //
    // Mark the first receive descriptor as available to the DMA to start
    // the receive processing.
    //
    g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus |= DES0_RX_CTRL_OWN;

    //
    // Reset the counters that are incremented by SysTick.
    //
    g_ui32Ticks = 0;
    g_ui32PeriodicTimer = 0;
    g_ui32ARPTimer = 0;

    //
    // Setup SysTick.
    //
    HWREG(NVIC_ST_RELOAD) = (ui32Clock / SYSTICKHZ) - 1;
    HWREG(NVIC_ST_CTRL) = (NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_INTEN |
                           NVIC_ST_CTRL_ENABLE);
}
//*****************************************************************************
//
//! Configures the Ethernet controller.
//!
//! This function configures the Ethernet controller, preparing it for use by
//! the boot loader.
//!
//! \return None.
//
//*****************************************************************************
void
ConfigureEnet(void)
{
    //
    // Make sure the main oscillator is enabled because this is required by
    // the PHY.  The system must have a 25MHz crystal attached to the OSC
    // pins.  The SYSCTL_MOSC_HIGHFREQ parameter is used when the crystal
    // frequency is 10MHz or higher.
    //
    HWREG(SYSCTL_MOSCCTL) = SYSCTL_MOSC_HIGHFREQ;

    //
    // Delay while the main oscillator starts up.
    //
    Delay(5242880);

    MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                            SYSCTL_OSC_MAIN |
                            SYSCTL_USE_PLL |
                            SYSCTL_CFG_VCO_480), 120000000);


#ifdef ENET_ENABLE_LEDS
    //
    // PF1/PK4/PK6 are used for Ethernet LEDs.
    //
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
    ROM_GPIOPinConfigure(GPIO_PF1_EN0LED2);
    ROM_GPIOPinConfigure(GPIO_PK4_EN0LED0);
    ROM_GPIOPinConfigure(GPIO_PK6_EN0LED1);

    //
    // Make the pin(s) be peripheral controlled.
    //
    ROM_GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_1, GPIO_DIR_MODE_HW);
    ROM_GPIODirModeSet(GPIO_PORTK_BASE, GPIO_PIN_4|GPIO_PIN_6, GPIO_DIR_MODE_HW);

    //
    // Set the pad(s) for standard push-pull operation.
    //
    ROM_GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_1, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
    ROM_GPIOPadConfigSet(GPIO_PORTK_BASE, GPIO_PIN_4|GPIO_PIN_6, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
#endif

    //
    // Enable and reset the Ethernet modules.
    //
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);

    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))
    {
    }

}

//*****************************************************************************
//
//! Starts the update process via BOOTP.
//!
//! This function starts the Ethernet firmware update process.  The BOOTP
//! (as defined by RFC951 at http://tools.ietf.org/html/rfc951) and TFTP (as
//! defined by RFC1350 at http://tools.ietf.org/html/rfc1350) protocols are
//! used to transfer the firmware image over Ethernet.
//!
//! \return Never returns.
//
//*****************************************************************************
void
UpdateBOOTP(void)
{
    //
    // Get the size of flash.
    //
    g_ui32FlashEnd =  ROM_SysCtlFlashSizeGet();
#ifdef FLASH_RSVD_SPACE
    g_ui32FlashEnd -= FLASH_RSVD_SPACE;
#endif

    //
    // Perform the common Ethernet configuration. The frequency should
    // match whatever the application sets the system clock.
    //
    EnetReconfig(120000000);

    //
    // Main Application Loop.
    //
    while(1)
    {
        uint32_t ui32Temp;

        //
        // See if there is a packet waiting to be read.
        //
        if(!(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &
             DES0_RX_CTRL_OWN))
        {
            //
            // Read the packet from the Ethernet controller.
            //
            uip_len = PacketReceive(uip_buf, UIP_CONF_BUFFER_SIZE);

            //
            // See if this is an IP packet.
            //
            if((uip_len != 0) &&
               (((struct uip_eth_hdr *)&uip_buf[0])->type ==
                HTONS(UIP_ETHTYPE_IP)))
            {
                //
                // Update the ARP tables based on this packet.
                //
                uip_arp_ipin();

                //
                // Process this packet.
                //
                uip_input();

                //
                // See if the processing of this packet resulted in a packet to be
                // sent.
                //
                if(uip_len > 0)
                {
                    //
                    // Update the ARP tables based on the packet to be sent.
                    //
                    uip_arp_out();

                    //
                    // Send the packet.
                    //
                    PacketTransmit(uip_buf, uip_len);

                    //
                    // Indicate that the packet has been sent.
                    //
                    uip_len = 0;
                }
            }

            //
            // See if this is an ARP packet.
            //
            else if((uip_len != 0) &&
                    (((struct uip_eth_hdr *)&uip_buf[0])->type ==
                     HTONS(UIP_ETHTYPE_ARP)))
            {
                //
                // Process this packet.
                //
                uip_arp_arpin();

                //
                // See if the processing of this packet resulted in a packet to be
                // sent.
                //
                if(uip_len > 0)
                {
                    //
                    // Send the packet.
                    //
                    PacketTransmit(uip_buf, uip_len);

                    //
                    // Indicate that the packet has been sent.
                    //
                    uip_len = 0;
                }
            }
        }

        //
        // See if the periodic timer has expired.
        //
        if(g_ui32PeriodicTimer > UIP_PERIODIC_TIMER_MS)
        {
            //
            // Reset the periodic timer.
            //
            g_ui32PeriodicTimer = 0;

            //
            // Loop through the UDP connections.
            //
            for(ui32Temp = 0; ui32Temp < UIP_UDP_CONNS; ui32Temp++)
            {
                //
                // Perform the periodic processing on this UDP connection.
                //
                uip_udp_periodic(ui32Temp);

                //
                // See if the periodic processing of this connection resulted in a
                // packet to be sent.
                //
                if(uip_len > 0)
                {
                    //
                    // Update the ARP tables based on the packet to be sent.
                    //
                    uip_arp_out();

                    //
                    // Send the packet.
                    //
                    PacketTransmit(uip_buf, uip_len);

                    //
                    // Indicate that the packet has been sent.
                    //
                    uip_len = 0;
                }
            }
        }

        //
        // See if the ARP timer has expired.
        //
        if(g_ui32ARPTimer > UIP_ARP_TIMER_MS)
        {
            //
            // Reset the ARP timer.
            //
            g_ui32ARPTimer = 0;

            //
            // Perform periodic processing on the ARP table.
            //
            uip_arp_timer();
        }
    }
}

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif