This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Team,
We would like to analyze the flash chip - S28HS512T. In SDR octal mode, i.e., 8s-8s-8s protocol.
Attached is the sysconfig file tried at our end. Using this configuration, the control gets stuck at status register read operation, since the value of status register is 0xFF.
/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM243x@08.05.00"
* @versions {"tool":"1.15.0+2826"}
*/
/**
* Import the modules used in this configuration.
*/
const flash = scripting.addModule("/board/flash/flash", {}, false);
const flash1 = flash.addInstance();
const ddr = scripting.addModule("/drivers/ddr/ddr", {}, false);
const ddr1 = ddr.addInstance();
const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1 = gpio.addInstance();
const mmcsd = scripting.addModule("/drivers/mmcsd/mmcsd", {}, false);
const mmcsd1 = mmcsd.addInstance();
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
/**
* Write custom configuration values to the imported modules.
*/
flash1.$name = "CONFIG_FLASH0";
flash1.idNumBytes = 5;
flash1.flashPageProgTimeout = 510;
flash1.strDtr_isAddrReg = false;
flash1.protocol = "8s_8s_8s";
flash1.cmdRd = "0xEC";
flash1.peripheralDriver.$name = "CONFIG_OSPI0";
flash1.peripheralDriver.dmaEnable = true;
flash1.peripheralDriver.inputClkFreq = 100000000;
flash1.peripheralDriver.phyEnable = true;
flash1.peripheralDriver.OSPI.$assign = "OSPI0";
flash1.peripheralDriver.OSPI.CLK.$assign = "ball.N20";
flash1.peripheralDriver.OSPI.CSn0.$assign = "ball.L19";
flash1.peripheralDriver.OSPI.DQS.$assign = "ball.N19";
flash1.peripheralDriver.OSPI.D7.$assign = "ball.M17";
flash1.peripheralDriver.OSPI.D6.$assign = "ball.N18";
flash1.peripheralDriver.OSPI.D5.$assign = "ball.P20";
flash1.peripheralDriver.OSPI.D4.$assign = "ball.P21";
flash1.peripheralDriver.OSPI.D3.$assign = "ball.M21";
flash1.peripheralDriver.OSPI.D2.$assign = "ball.M20";
flash1.peripheralDriver.OSPI.D1.$assign = "ball.M18";
flash1.peripheralDriver.OSPI.D0.$assign = "ball.M19";
ddr1.$name = "CONFIG_DDR0";
gpio1.$name = "OSPI_RSTN";
gpio1.pinDir = "OUTPUT";
gpio1.GPIO.$assign = "GPIO0";
gpio1.GPIO.gpioPin.$assign = "ball.K17";
mmcsd1.$name = "CONFIG_MMCSD0";
mmcsd1.moduleSelect = "MMC0";
mmcsd1.MMC0.$assign = "MMC0";
const udma = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1 = udma.addInstance({}, false);
udma1.$name = "CONFIG_UDMA0";
flash1.peripheralDriver.udmaDriver = udma1;
debug_log.enableUartLog = true;
debug_log.uartLog.$name = "CONFIG_UART_CONSOLE";
debug_log.uartLog.UART.$assign = "USART0";
debug_log.uartLog.UART.RXD.$assign = "ball.D15";
debug_log.uartLog.UART.TXD.$assign = "ball.C16";
mpu_armv71.$name = "CONFIG_MPU_REGION0";
mpu_armv71.size = 31;
mpu_armv71.attributes = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute = false;
mpu_armv72.$name = "CONFIG_MPU_REGION1";
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv72.size = 15;
mpu_armv73.$name = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr = 0x41010000;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv73.size = 15;
mpu_armv74.$name = "CONFIG_MPU_REGION3";
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr = 0x70000000;
mpu_armv74.size = 21;
mpu_armv75.$name = "CONFIG_MPU_REGION5";
mpu_armv75.baseAddr = 0x80000000;
mpu_armv75.size = 31;
Could you please share the 8s-8s-8s sys config file?
Thanks,
Akshay
Hi Akshay,
There are a lot of changes required at driver level for this flash to be functional in 8s-8s-8s mode.
Here are Flash driver related changes -
source/board/flash/ospi/flash_nor_ospi.c | 14 ++++++++++---- source/drivers/ospi/v0/ospi_v0.c | 9 ++++++--- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/source/board/flash/ospi/flash_nor_ospi.c b/source/board/flash/ospi/flash_nor_ospi.c index 981bc0478b..f8ea6e569d 100644 --- a/source/board/flash/ospi/flash_nor_ospi.c +++ b/source/board/flash/ospi/flash_nor_ospi.c @@ -127,7 +127,7 @@ static int32_t Flash_norOspiWaitReady(Flash_Config *config, uint32_t timeOut) uint8_t dummyBits = 0; /* Do RDSR based on xspi WIP status */ - if((devCfg->xspiWipRdCmd != 0x00) && (obj->currentProtocol == FLASH_CFG_PROTO_8D_8D_8D)) + if((devCfg->xspiWipRdCmd != 0x00) && ((obj->currentProtocol == FLASH_CFG_PROTO_8D_8D_8D)||(obj->currentProtocol == FLASH_CFG_PROTO_8S_8S_8S))) { /* Check XSPI WIP configuration */ cmd = devCfg->xspiWipRdCmd; @@ -818,6 +818,12 @@ static int32_t Flash_norOspiReadId(Flash_Config *config) cmdAddr = 0U; idNumBytes = 4; /* Can't read odd bytes in octal DDR */ } + else if(obj->currentProtocol == FLASH_CFG_PROTO_8S_8S_8S) + { + dummyBits = 2; + cmdAddr = 0U; + idNumBytes = 4; + } else { /* default config */ @@ -1175,15 +1181,15 @@ static int32_t Flash_norOspiOpen(Flash_Config *config, Flash_Params *params) status += Flash_norOspiSetModeDummy(config, obj->ospiHandle); /* Set RD Capture Delay by reading ID */ - uint32_t readDataCapDelay = 4U; + uint32_t readDataCapDelay = 0U; OSPI_setRdDataCaptureDelay(obj->ospiHandle, readDataCapDelay); status = Flash_norOspiReadId(config); - while((status != SystemP_SUCCESS) && (readDataCapDelay > 0U)) + while((status != SystemP_SUCCESS) && (readDataCapDelay < 4U)) { - readDataCapDelay--; OSPI_setRdDataCaptureDelay(obj->ospiHandle, readDataCapDelay); status = Flash_norOspiReadId(config); + readDataCapDelay++; } /* Enable PHY if attack vector present and PHY mode is enabled */ diff --git a/source/drivers/ospi/v0/ospi_v0.c b/source/drivers/ospi/v0/ospi_v0.c index baa7408e0b..a3143b5b70 100644 --- a/source/drivers/ospi/v0/ospi_v0.c +++ b/source/drivers/ospi/v0/ospi_v0.c @@ -744,11 +744,14 @@ void OSPI_setProtocol(OSPI_Handle handle, uint32_t protocol) /* Set transfer lines for sending data */ CSL_REG32_FINS(&pReg->DEV_INSTR_WR_CONFIG_REG, OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD, data); - if(dtr) + //if(dtr) { - if(protocol == OSPI_NOR_PROTOCOL(8,8,8,1)) + if(protocol == OSPI_NOR_PROTOCOL(8,8,8,1)||protocol == OSPI_NOR_PROTOCOL(8,8,8,0)) { - OSPI_enableDDR(handle); + if(protocol == OSPI_NOR_PROTOCOL(8,8,8,1)) + { + OSPI_enableDDR(handle); + } OSPI_setDualOpCodeMode(handle); } if(protocol == OSPI_NOR_PROTOCOL(4,4,4,1))
After the driver changes, ensure to rebuild the libs like this - https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/latest/exports/docs/api_guide_am243x/MAKEFILE_BUILD_PAGE.html#autotoc_md380
After the libs are rebuild, you would also need some obvious changes in the syscfg like this -
Hope it helps.
Best Regards,
Aakash
Hi Aakash Kedia,
Thanks for looking into the problem and sharing the steps to modify the driver.
We shall test the same and let you know.
Thanks,
Akshay