MSPM0G3507: Forcing initial SPI clock state for active low clock configurations

Hello,

I noticed that when using a manual GPIO chip select the SPI controller doesn't set the clock line high on initialization when configured for CPOL 1 PHA1 (DL_SPI_FRAME_FORMAT_MOTO3_POL1_PHA1)

I understand that if the chip select is handled outside of the spi controller there's no way for the controller to know when it's intended to be active outside of writing something to the TX FIFO, but any ideas on how to get this state to be correct when using a GPIO chip select?

As you can see in the picture the spi clock is low until data is written to the fifo and then it the clock polarity and phase start working correctly.

Munan