LP-MSPM0G3507: Unable to see continuous clock on SPI

Hello Gupta,

Because of the hardware physical property of SPI interface, it can support sending or receiving max 16-bit data each time. 

It means that during the interval time between first time and second time data transmission, the CLK will keep low level. 

About more details about SPI transmission, I recommend you can read our TRM which can be downloaded from:MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual (Rev. A)

Best Regards,

Janz Bai

2) The hardware Chip Selects are applied to individual frames (bytes in your case) [Ref TRM (SLAU846A) Sec 17.2.3.1]. To frame the entire transaction, you need to change "Frame Format" to "Motorola 3-wire" then configure that pin (PB17 in the example) as a GPIO and control it directly in your code. 

1) I expect at least some (maybe all) of the gap between bytes is due to (2), so try that first and see what you get.

Hi Bruce,

Tried the option, as you mentioned in (2), but still the gap between frames is there even we control CS pin manually.

Sorry, then I don't know the answer to (1), and I haven't experimented with it.

A brief search of the Forum ("mspm0 spi gap") turned up this item:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1369354/mspm0l1306-32-bit-data-spi-frame-size-with-mspm0-l-series-mcu

The discussion is about PACKEN, but in the final response Zoey Wei reports "But there is still a 4 us clock gap between two 16bit operations @ 500k SPI clock.". Given that (I think) Zoey has access to the designers, I don't know whether this was an observation or a fact about the SPI unit.

I don't think I've worked with an SPI Peripheral that cared much about gaps in a transaction. If you can describe what you're trying to accomplish, maybe there's a different way of doing it.

Since the master controls the clock, the peripheral should not care about gaps in the clock as long as the CS stays active. What are you trying to control?

Worse comes to worse, you may have to bit-bang it.

Hello Gupta,

As Zoey mentioned in her E2E (Bruce shared with you), even you enable PACKEN, there is still a 4 us clock gap between two 16bits operations (500k SPI) because FIFO of SPI is 16bits. And the gap is found in Zoey's test. As Bruce mentioned, you can use GPIO to simulate CS to let it not toggle, but due to the physical hardware limitation ( the FIFO length), the SPI CLK will occur gap in SPI usage.

Best Regards,

Janz Bai

Thanks Janz. So I understand that the gap is an artifact of the SPI unit, i.e. the time it takes to load from the FIFO to the shift register, and is a known duration (perhaps based on SCK frequency).

While searching, I also ran across this thread:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1180685/msp-exp432e401y-delay-between-bytes-when-transmitting-over-spi/4447263

Where the OP came up with a solution for a particular case, assuming that (a) the gap is always <this long> and (b) the MOSI pin holds the value of the final bit during that time. The application there was a Neopixel array, but there may be others as well.